The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware, although Opus Systems offered a product based on the Clipper as part of its Personal Mainframe range. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.
| Attributes | Values |
|---|
| rdf:type
| |
| rdfs:label
| - Clipper-Prozessor (de)
- Clipper architecture (en)
- Architettura Clipper (it)
|
| rdfs:comment
| - The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware, although Opus Systems offered a product based on the Clipper as part of its Personal Mainframe range. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems. (en)
- Der Clipper-Prozessor war ein 32-Bit-RISC-Prozessor von Fairchild Semiconductor. Im Vergleich zu anderen RISC-Prozessoren verfügte der Clipper über einen relativ umfangreichen Befehlssatz, der durch in den Prozessor integrierte Funktionsbibliotheken realisiert wurde. Zunächst unter der Bezeichnung C100 produzierte Fairchild Semiconductor den aus drei Chips bestehenden Prozessor. Der CPU-Chip wurde durch zwei sogenannte CAMMUs unterstützt, Cache und MMU-Einheiten (Cache and MMU), je eine für Befehle und eine für Daten. Geliefert wurden die drei Chips auf einer Platine als Modul montiert. (de)
- Clipper è un'architettura di microprocessori a 32 bit con un set di istruzioni di tipo RISC sviluppata da Fairchild Semiconductor. Questa architettura non ha mai avuto molto successo e gli unici computer basati su questa architettura sono stati prodotti da e da . I primi processori Clipper sono stati sviluppati e prodotti da Fairchild ma, nel 1987 la divisione responsabile del progetto è stata venduta a Intergraph che ha continuato lo sviluppo dei processori per i suoi sistemi. (it)
|
| differentFrom
| |
| name
| |
| foaf:depiction
| |
| dcterms:subject
| |
| Wikipage page ID
| |
| Wikipage revision ID
| |
| Link from a Wikipage to another Wikipage
| |
| Link from a Wikipage to an external page
| |
| sameAs
| |
| dbp:wikiPageUsesTemplate
| |
| thumbnail
| |
| caption
| - Intergraph Clipper C4 CPU (en)
|
| design
| |
| introduced
| |
| has abstract
| - Der Clipper-Prozessor war ein 32-Bit-RISC-Prozessor von Fairchild Semiconductor. Im Vergleich zu anderen RISC-Prozessoren verfügte der Clipper über einen relativ umfangreichen Befehlssatz, der durch in den Prozessor integrierte Funktionsbibliotheken realisiert wurde. Zunächst unter der Bezeichnung C100 produzierte Fairchild Semiconductor den aus drei Chips bestehenden Prozessor. Der CPU-Chip wurde durch zwei sogenannte CAMMUs unterstützt, Cache und MMU-Einheiten (Cache and MMU), je eine für Befehle und eine für Daten. Geliefert wurden die drei Chips auf einer Platine als Modul montiert. Der Clipper fand aufgrund relativ hoher Kosten trotz seiner guten Leistungsfähigkeit nur wenige Kunden. Zudem waren zum Zeitpunkt der Markteinführung 1986 bereits mehrere andere 32-Bit-Architekturen gut im Markt eingeführt, so dass eine relativ teure neue Architektur wenig Chancen hatte. Nachdem 1987 Fairchild Semiconductor durch National Semiconductor aufgekauft wurde, verschlechterte sich die Situation für den Clipper-Prozessor weiter, da National Semiconductor mit dem NS320xx bereits eine wenig erfolgreiche 32-Bit-Prozessorfamilie im eigenen Hause hatte. Die gesamte Clipper-Abteilung wurde daraufhin an den größten Clipper-Kunden, die Firma Intergraph, verkauft. Intergraph stellte 1988 den C300 und 1990 den C400 vor. Arbeiten an einem weiteren Nachfolger wurden später eingestellt. Diverse Patente, speziell auf Techniken die in den CAMMUs verwendet wurden, führten später zu einem Rechtsstreit zwischen Intergraph und Intel, sowie weiteren Firmen, da viele neuere Prozessoren diese Techniken einsetzen. (de)
- The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware, although Opus Systems offered a product based on the Clipper as part of its Personal Mainframe range. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems. The Clipper architecture used a simplified instruction set compared to earlier CISC architectures, but it did incorporate some more complicated instructions than were present in other contemporary RISC processors. These instructions were implemented in a so-called Macro Instruction ROM within the Clipper CPU. This scheme allowed the Clipper to have somewhat higher code density than other RISC CPUs. (en)
- Clipper è un'architettura di microprocessori a 32 bit con un set di istruzioni di tipo RISC sviluppata da Fairchild Semiconductor. Questa architettura non ha mai avuto molto successo e gli unici computer basati su questa architettura sono stati prodotti da e da . I primi processori Clipper sono stati sviluppati e prodotti da Fairchild ma, nel 1987 la divisione responsabile del progetto è stata venduta a Intergraph che ha continuato lo sviluppo dei processori per i suoi sistemi. L'architettura Clipper utilizza un set semplificato di istruzioni rispetto ai processori CISC dell'epoca ma possedeva alcune istruzioni molto complesse rispetto alle architetture RISC dell'epoca. Le istruzioni complesse erano implementate tramite l'utilizzo di istruzioni elementari del processore. In sostanza le istruzioni complesse venivano tradotte tramite una ROM interna in una serie di istruzioni elementari che il processore eseguiva in modo nativo. Questo consentiva al clipper di avere una densità di codice molto più elevata degli altri processori RISC. (it)
|
| bits
| |
| gold:hypernym
| |
| prov:wasDerivedFrom
| |
| page length (characters) of wiki page
| |
| foaf:isPrimaryTopicOf
| |
| is differentFrom
of | |
![[RDF Data]](/fct/images/sw-rdf-blue.png)
![[cxml]](/fct/images/cxml_doc.png)
![[csv]](/fct/images/csv_doc.png)
![[text]](/fct/images/ntriples_doc.png)
![[turtle]](/fct/images/n3turtle_doc.png)
![[ld+json]](/fct/images/jsonld_doc.png)
![[rdf+json]](/fct/images/json_doc.png)
![[rdf+xml]](/fct/images/xml_doc.png)
![[atom+xml]](/fct/images/atom_doc.png)
![[html]](/fct/images/html_doc.png)
