About: OpenRISC 1200

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The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1] Archived 2017-01-15 at the Wayback Machine. A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).

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rdf:type	software yago:WikicatOpenMicroprocessors yago:WikicatSoftMicroprocessors yago:Artifact100021939 yago:Chip103020034 yago:Conductor103088707 yago:Device103183080 yago:Instrumentality103575240 yago:Microprocessor103760310 yago:Object100002684 yago:PhysicalEntity100001930 yago:SemiconductorDevice104171831 yago:Whole100003553
rdfs:label	OpenRISC 1200 (en)
rdfs:comment	The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1] Archived 2017-01-15 at the Wayback Machine. A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL). (en)
foaf:depiction
dcterms:subject	Soft microprocessors Open microprocessors
Wikipage page ID	16732958 (xsd:integer)
Wikipage revision ID	1119679166 (xsd:integer)
Link from a Wikipage to another Wikipage	Programmable interrupt controller Application-specific integrated circuit Verilog Soft microprocessors CoreMark Free and Open Source Silicon Foundation GNU Compiler Collection GNU Lesser General Public License Linux kernel Translation lookaside buffer CPU cache UClibc GNU toolchain ARM architecture Open microprocessors Dhrystone Hardware description language Harvard architecture Wishbone (computer bus) IP core Digital signal processor Field-programmable gate array Instruction set architecture Newlib Open-source license OpenRISC OpenCores Soft microprocessor RISC IEEE floating-point standard Memory management units Multiply–accumulate
Link from a Wikipage to an external page	http://www.orsoc.se/%3Fs=devkit https://web.archive.org/web/20080330225652/http:/www.asisi.co.uk/openrisc/openrisc.html https://web.archive.org/web/20100210225548/http:/www.opencores.org/openrisc,or1200 https://web.archive.org/web/20120311102053/http:/opencores.org/ocsvn/openrisc/openrisc/trunk/or1200/doc/openrisc1200_spec.pdf https://web.archive.org/web/20170115094656/http:/opencores.org/openrisc,architecture http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200/doc/openrisc1200_spec.pdf http://opencores.org/openrisc,architecture http://www.opencores.org/openrisc,or1200 http://librecores.org
sameAs	OpenRISC 1200 OpenRISC 1200 OpenRISC 1200 OpenRISC 1200 OpenRISC 1200
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thumbnail	wiki-commons:Special:FilePath/OR1200.png?width=300
date	2010-02-10 (xsd:date) 2012-03-11 (xsd:date) 2017-01-15 (xsd:date)
url	https://web.archive.org/web/20100210225548/http:/www.opencores.org/openrisc,or1200 https://web.archive.org/web/20120311102053/http:/opencores.org/ocsvn/openrisc/openrisc/trunk/or1200/doc/openrisc1200_spec.pdf https://web.archive.org/web/20170115094656/http:/opencores.org/openrisc,architecture
has abstract	The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1] Archived 2017-01-15 at the Wayback Machine. A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL). (en)
gold:hypernym	Implementation
prov:wasDerivedFrom	wikipedia-en:OpenRISC_1200?oldid=1119679166&ns=0
page length (characters) of wiki page	6260 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:OpenRISC_1200
is Link from a Wikipage to another Wikipage of	List of open-source hardware Openrisc 1200 OpenRISC Or1200 OR1200
is Wikipage redirect of	Openrisc 1200 Or1200 OR1200
is foaf:primaryTopic of	wikipedia-en:OpenRISC_1200

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