About: Process–architecture–optimization model

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Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly.

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rdfs:label	プロセス・アーキテクチャ最適化モデル (ja) Process–architecture–optimization model (en) 制程-架构-优化模型 (zh)
rdfs:comment	Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly. (en) プロセス・アーキテクチャ最適化（英語: Process-Architecture-Optimization model）は、Intelが2016年に採用したプロセッサ開発モデルである。この3フェーズモデルでは、ダイの縮小の後に、マイクロアーキテクチャの変更が行われ、その後、最適化が行われる。これは、2006年にIntelが採用した2フェーズのTick-tockモデルを置き換えるものである。Intelによると、以前のモデルは、現在では持続可能なものではなくなっている。内はマイクロアーキテクチャ名斜体は将来の計画 (ja) 制程-架构-优化模型（英語：Process–architecture–optimization model）是英特尔于2016年开始采用的针对其中央处理器的开发模型。在这种3个阶段的模式下，每一次中央处理器的制程升级之后将会对微架构进行升级，然后对微架构进行一次或多次的优化。它取代了英特尔以前采用的Tick-Tock模型，据英特尔称，Tick-Tock模型在经济上已不可持续，因为提升制程工艺的研发费用变得比以前多得多。 (zh)
dcterms:subject	Intel x86 microprocessors Technology strategy
Wikipage page ID	56916379 (xsd:integer)
Wikipage revision ID	1123857905 (xsd:integer)
Link from a Wikipage to another Wikipage	Rocket Lake Tick–tock model 10 nm process 14 nm process Comet Lake Coffee Lake Golden Cove Skylake (microarchitecture) Microarchitecture 5 nm process 7 nm process Broadwell (microarchitecture) Tiger Lake Willow Cove Alder Lake Palm Cove (microarchitecture) Central processing unit Die shrink List of Intel CPU microarchitectures Intel x86 microprocessors Kaby Lake Sunny Cove (microarchitecture) Technology strategy Cypress Cove (microarchitecture) Ice Lake (microprocessor) Intel Microprocessor Cannon Lake (microprocessor) Raptor Lake Coffee Lake Refresh Intel 20A
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has abstract	Process–architecture–optimization is a development model for central processing units (CPUs) that Intel adopted in 2016. Under this three-phase (three-year) model, every microprocessor die shrink is followed by a microarchitecture change and then by one or more optimizations. It replaced the two-phase (two-year) tick–tock model that Intel adopted in 2006. The tick–tock model was no longer economically sustainable, according to Intel, because production of ever smaller dies becomes ever more costly. (en) プロセス・アーキテクチャ最適化（英語: Process-Architecture-Optimization model）は、Intelが2016年に採用したプロセッサ開発モデルである。この3フェーズモデルでは、ダイの縮小の後に、マイクロアーキテクチャの変更が行われ、その後、最適化が行われる。これは、2006年にIntelが採用した2フェーズのTick-tockモデルを置き換えるものである。Intelによると、以前のモデルは、現在では持続可能なものではなくなっている。内はマイクロアーキテクチャ名斜体は将来の計画 (ja) 制程-架构-优化模型（英語：Process–architecture–optimization model）是英特尔于2016年开始采用的针对其中央处理器的开发模型。在这种3个阶段的模式下，每一次中央处理器的制程升级之后将会对微架构进行升级，然后对微架构进行一次或多次的优化。它取代了英特尔以前采用的Tick-Tock模型，据英特尔称，Tick-Tock模型在经济上已不可持续，因为提升制程工艺的研发费用变得比以前多得多。 (zh)
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page length (characters) of wiki page	6064 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Process–architecture–optimization_model
is Link from a Wikipage to another Wikipage of	Process-Architecture-Optimization model Process-architecture-optimization model Sapphire Rapids Tick–tock model Emerald Rapids Process-Architecture-Optimization Tiger Lake List of Intel CPU microarchitectures Kaby Lake Intel Microprocessor chronology Cannon Lake (microprocessor) Sierra Forest
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