About: Process corners

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In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin.

Attributes	Values
rdf:type	yago:Artifact100021939 yago:Circuit103033362 yago:ComputerCircuit103084420 yago:Device103183080 yago:ElectricalDevice103269401 yago:Instrumentality103575240 yago:IntegratedCircuit103577090 yago:Object100002684 yago:PhysicalEntity100001930 yago:WikicatIntegratedCircuits building yago:Whole100003553
rdfs:label	Process corners (en)
rdfs:comment	In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin. (en)
dcterms:subject	Integrated circuits
Wikipage page ID	18648165 (xsd:integer)
Wikipage revision ID	1098527867 (xsd:integer)
Link from a Wikipage to another Wikipage	NMOS logic Nominal (value) Design of experiments Dopant Duty cycle Integrated circuit Integrated circuit layout Standard deviation SPICE Very-large-scale integration MOSFET Front end of line PMOS logic Wafer (electronics) Die (integrated circuit) Die shrink Integrated circuits BSIM Back end of line Tapeout Circuit extraction FET Microprocessor Catastrophic failure Product binning Slew rate Semiconductor Shmoo plot Simulation Skew lines Digital logic 90nm Carrier mobility Silicon wafer Latch (electronics) Clean-room Semiconductor fabrication
Link from a Wikipage to an external page	http://www.google.com/patents%3Fid=EKwOAAAAEBAJ
sameAs	Process corners Process corners Process corners Process corners
dbp:wikiPageUsesTemplate	dbt:Reflist dbt:Short_description dbt:Use_American_English
has abstract	In semiconductor manufacturing, a process corner is an example of a design-of-experiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin. To verify the robustness of an integrated circuit design, semiconductor manufacturers will fabricate corner lots, which are groups of wafers that have had process parameters adjusted according to these extremes, and will then test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination (two or sometimes all three together) in a process called characterization. The results of these tests are plotted using a graphing technique known as a shmoo plot that indicates clearly the boundary limit beyond which a device begins to fail for a given combination of these environmental conditions. Corner-lot analysis is most effective in digital electronics because of the direct effect of process variations on the speed of transistor switching during transitions from one logic state to another, which is not relevant for analog circuits, such as amplifiers. (en)
gold:hypernym	Example
prov:wasDerivedFrom	wikipedia-en:Process_corners?oldid=1098527867&ns=0
page length (characters) of wiki page	7127 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Process_corners
is Link from a Wikipage to another Wikipage of	On-chip variation PVT Adaptive voltage scaling Semiconductor device fabrication Static timing analysis Process variation (semiconductor) Signoff (electronic design automation) Very Large Scale Integration
is Wikipage redirect of	On-chip variation
is foaf:primaryTopic of	wikipedia-en:Process_corners

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