Project Denver is the codename of a microarchitecture designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128 MB cache stored in main memory". Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
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| - Project Denver (en)
- Project Denver (zh)
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| - Project Denver是NVIDIA公司於2011年1月5日在CES 2011上發表的採用ARM架構的微處理器，中文含義為“丹佛計畫”。 2011年1月5日NVIDIA宣佈將自行設計與研發基於ARM架構的桌上型電腦CPU，産品代號Project Denver（丹佛計畫）。其處理器能夠支援微軟下一代桌面系統Windows 8以及行動平臺上的Google Android、苹果iOS等。相比之前的Tegra產品，NVIDIA總裁表示这将是一颗高度定制化的“ARM兼容CPU”，即获得ARM指令集授权，但处理器微架构则完全由NVIDIA自行开发，以更高性能面向桌面、服务器甚至高性能计算市场。屆時NVIDIA基於ARM架構的處理器將在市場上與Intel和AMD等基於X86架構的處理器直接競爭。 2014年1月6日，NVIDIA宣布了丹佛计划的首个成果——64位版Tegra K1。 (zh)
- Project Denver is the codename of a microarchitecture designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128 MB cache stored in main memory". Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC). (en)
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| - Nvidia Carmel (en)
- Nvidia Denver 1/2 (en)
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| - ARMv8-A (en)
- ARMv8.2-A (en)
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| - Project Denver is the codename of a microarchitecture designed by Nvidia that implements the ARMv8-A 64/32-bit instruction sets using a combination of simple hardware decoder and software-based binary translation (dynamic recompilation) where "Denver's binary translation layer runs in software, at a lower level than the operating system, and stores commonly accessed, already optimized code sequences in a 128 MB cache stored in main memory". Denver is a very wide in-order superscalar pipeline. Its design makes it suitable for integration with other SIPs cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC). Project Denver is targeted at mobile computers, personal computers, servers, as well as supercomputers. Respective cores have found integration in the Tegra SoC series from Nvidia. Initially Denver cores was designed for the process node (Tegra model T132 aka "Tegra K1"). Denver 2 was an improved design that built for the smaller, more efficient node. (Tegra model T186 aka "Tegra X2"). In 2018, Nvidia released an improved design (codename: "Carmel", based on ARMv8 (64-bit; variant: ARM-v8.2 with 10-way superscalar, functional safety, dual execution, parity & ECC) got integrated into the Tegra Xavier SoC offering a total of 8 cores (or 4 dual-core pairs). The Carmel CPU core supports full Advanced SIMD (ARM NEON), VFP (Vector Floating Point), and ARMv8.2-FP16. First published testings of Carmel cores integrated in the Jetson AGX development kit by third party experts took place in September 2018 and indicated a noticeably increased performance as should expected for this real world physical manifestation compared to predecessors systems, despite all doubts the used quickness of such a test setup in general an in particular implies. The Carmel design can be found in the Tegra model T194 ("Tegra Xavier") that is designed with a 12 nm structure size. (en)
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