About: Quasi-delay-insensitive circuit

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In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete.

Attributes	Values
rdfs:label	Quasi-delay-insensitive circuit (en)
rdfs:comment	In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete. (en)
foaf:depiction
dcterms:subject	Electrical circuits
Wikipage page ID	2817767 (xsd:integer)
Wikipage revision ID	1120549254 (xsd:integer)
Link from a Wikipage to another Wikipage	Monotonic function Delay insensitive circuit Domino logic Inverter (logic gate) Combinational logic OR gate Communications protocol GitHub Clock gating Communicating sequential processes Pipeline (computing) Electrical circuits Tony Hoare Hazard (logic) Edsger W. Dijkstra Mutual exclusivity Asynchronous circuit AND gate Bipartite graph Boolean expression C-element Philips Guarded Command Language Short circuit Digital logic Process variation (semiconductor) Ring oscillator Turing-complete
Link from a Wikipage to an external page	http://vlsi.cornell.edu/~fang/hackt/%7Caccess-date=6 http://www.cs.upc.edu/~jordicf/petrify/%7Cwebsite=UPC/DAC https://docs.google.com/presentation/d/11w59jPf3YmbpAyRkBiP9-37KjHjU1f4FMW0M1xEFANQ/edit%3Fusp=sharing https://docs.google.com/presentation/d/18l8TIW6aAaCoH4oNOyYrw2CpQcIsMxm8fHbzFJZQygA/edit%3Fusp=sharing https://docs.google.com/presentation/d/1DCYdx8V4Lzd7LVsJwxADBroLFX7OZw581bBITbUX41Y/edit%3Fusp=sharing https://docs.google.com/presentation/d/1FaBkruruNTbEDsMKMVjUWUYpmTwuCIwyiB2F0bTZ0V8/edit%3Fusp=sharing https://docs.google.com/presentation/d/1IfZwFHvdMxfG4m6_01otx2CuJLPcFdncUEoJ1n5sNUk/edit%3Fusp=sharing https://docs.google.com/presentation/d/1rItsWZD-ENX9_8ONdHM1YpxLgvaYDIfrjsJIrxHWX2g/edit%3Fusp=sharing https://docs.google.com/presentation/d/1rhX8NpYjSPOusMYqh9mkT4VHOUP-ZH7LzGWJoKh6vrs/edit%3Fusp=sharing https://github.com/asyncvlsi/act%7Caccess-date=14 https://github.com/kristofferkoch/Balsa%7Caccess-date=6 https://github.com/nbingham1/hsesim%7Caccess-date=14
sameAs	Quasi-delay-insensitive circuit Quasi-delay-insensitive circuit Quasi-delay-insensitive circuit
dbp:wikiPageUsesTemplate	dbt:Anchor dbt:Cite_web dbt:Cleanup dbt:Main dbt:Reflist dbt:Para
thumbnail	wiki-commons:Special:FilePath/QDI_Pipeline.svg?width=300
date	December 2021 (en)
group	timing (en) verification (en) layout (en) chips (en) sizing (en) synthesis (en)
reason	that the article uses very unusual style of citation: it excessively relies on the html-tag attribute . It would probably be better to use a numeric style. Please discuss. (en)
has abstract	In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete. (en)
prov:wasDerivedFrom	wikipedia-en:Quasi-delay-insensitive_circuit?oldid=1120549254&ns=0
page length (characters) of wiki page	34764 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Quasi-delay-insensitive_circuit
is Link from a Wikipage to another Wikipage of	Quasi-delay-insensitive Quasi Delay Insensitive Asynchronous system Asynchronous circuit Guarded Command Language Signal transition graphs QDI Quasi-Delay-Insensitive Isochronic fork Speed Independent
is Wikipage redirect of	Quasi-delay-insensitive Quasi Delay Insensitive QDI Quasi-Delay-Insensitive Isochronic fork Speed Independent
is foaf:primaryTopic of	wikipedia-en:Quasi-delay-insensitive_circuit

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