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About: Standard Parasitic Exchange Format     Goto   Sponge   NotDistinct   Permalink

An Entity of Type : yago:WikicatElectronicCircuitSimulators, within Data Space : dbpedia.demo.openlinksw.com associated with source document(s)

Type: yago:Artifact100021939yago:Device103183080yago:Instrumentality103575240yago:Machine103699975yago:Object100002684yago:PhysicalEntity100001930yago:Simulator104221823yago:Whole100003553yago:WikicatElectronicCircuitSimulators New Facet based on Instances of this Class

Standard Parasitic Exchange Format (SPEF) is an IEEE standard for representing parasitic data of wires in a chip in ASCII format. Non-ideal wires have parasitic resistance and capacitance that are captured by SPEF. These wires also have inductance that is not included in SPEF. SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation. SPEF is the most popular specification for parasitic exchange between different tools of EDA domain during any phase of design.