About: Stub Series Terminated Logic     Goto   Sponge   NotDistinct   Permalink

An Entity of Type : yago:SystemOfMeasurement113577171, within Data Space : dbpedia.demo.openlinksw.com associated with source document(s)
QRcode icon
http://dbpedia.demo.openlinksw.com/describe/?url=http%3A%2F%2Fdbpedia.org%2Fresource%2FStub_Series_Terminated_Logic&invfp=IFP_OFF&sas=SAME_AS_OFF

Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules. SSTL is primarily designed for driving the DDR (double-data-rate) SDRAM modules used in computer memory; however, it is also used in other applications, notably some PCI Express PHYs and other high-speed devices. Four voltage levels for SSTL are defined: SSTL_3 uses a reference of 0.45 * VDDQ (1.5 V). SSTL_2 and SSTL_18 reference a voltage that is exactly VDDQ / 2 (1.25 V and 0.9 V respectively).

AttributesValues
rdf:type
rdfs:label
  • Stub Series Terminated Logic (en)
rdfs:comment
  • Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules. SSTL is primarily designed for driving the DDR (double-data-rate) SDRAM modules used in computer memory; however, it is also used in other applications, notably some PCI Express PHYs and other high-speed devices. Four voltage levels for SSTL are defined: SSTL_3 uses a reference of 0.45 * VDDQ (1.5 V). SSTL_2 and SSTL_18 reference a voltage that is exactly VDDQ / 2 (1.25 V and 0.9 V respectively). (en)
dcterms:subject
Wikipage page ID
Wikipage revision ID
Link from a Wikipage to another Wikipage
Link from a Wikipage to an external page
sameAs
dbp:wikiPageUsesTemplate
has abstract
  • Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules. SSTL is primarily designed for driving the DDR (double-data-rate) SDRAM modules used in computer memory; however, it is also used in other applications, notably some PCI Express PHYs and other high-speed devices. Four voltage levels for SSTL are defined: * SSTL_3, 3.3 V, defined in EIA/JESD8-8 1996 * SSTL_2, 2.5 V, defined in EIA/JESD8-9B 2002 used in DDR among other things. * SSTL_18, 1.8 V, defined in EIA/JESD8-15A, used in DDR2 among other things. * SSTL_15, 1.5 V, used in DDR3 among other things. SSTL_3 uses a reference of 0.45 * VDDQ (1.5 V). SSTL_2 and SSTL_18 reference a voltage that is exactly VDDQ / 2 (1.25 V and 0.9 V respectively). SSTL_3 and SSTL_2 support two termination classes (50 ohm or 25 ohm load). SSTL_18 only supports one (25 ohm load). (en)
gold:hypernym
prov:wasDerivedFrom
page length (characters) of wiki page
foaf:isPrimaryTopicOf
is Link from a Wikipage to another Wikipage of
is Wikipage disambiguates of
is foaf:primaryTopic of
Faceted Search & Find service v1.17_git139 as of Feb 29 2024


Alternative Linked Data Documents: ODE     Content Formats:   [cxml] [csv]     RDF   [text] [turtle] [ld+json] [rdf+json] [rdf+xml]     ODATA   [atom+xml] [odata+json]     Microdata   [microdata+json] [html]    About   
This material is Open Knowledge   W3C Semantic Web Technology [RDF Data] Valid XHTML + RDFa
OpenLink Virtuoso version 08.03.3330 as of Mar 19 2024, on Linux (x86_64-generic-linux-glibc212), Single-Server Edition (378 GB total memory, 59 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software