A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an input is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the input could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.Not all faults can be analyzed using the stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model. Also, redundant circuits cannot be tested using this mo
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| - Stuck-at fault (en)
- 固定型故障 (zh)
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| - 固定型故障（stuck-at fault）也稱為黏著性故障，是信號或是針腳固定在邏輯的高電位、低電位，或是高阻态的，故障模擬器或是ATPG會用這故障來模擬集成电路中的製程瑕疵。在測試時，會將信號維持在高電位一段時間，確定此信號不會固定在低電位，也會將信號維持在低電位一段時間，確定此信號不會固定在高電位。 固定型故障只能用來分析部份的故障，針對靜態冒險（即分支信號）的補償信號會讓此信號無法用固定型故障模型進行測試，而冗餘型電路也無法用此模型進行測試，因為依照設計，若只有單一故障，不會因此影響輸出信號。 (zh)
- A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an input is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the input could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.Not all faults can be analyzed using the stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model. Also, redundant circuits cannot be tested using this mo (en)
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| - A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an input is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the input could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.Not all faults can be analyzed using the stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model. Also, redundant circuits cannot be tested using this model, since by design there is no change in any output as a result of a single fault. (en)
- 固定型故障（stuck-at fault）也稱為黏著性故障，是信號或是針腳固定在邏輯的高電位、低電位，或是高阻态的，故障模擬器或是ATPG會用這故障來模擬集成电路中的製程瑕疵。在測試時，會將信號維持在高電位一段時間，確定此信號不會固定在低電位，也會將信號維持在低電位一段時間，確定此信號不會固定在高電位。 固定型故障只能用來分析部份的故障，針對靜態冒險（即分支信號）的補償信號會讓此信號無法用固定型故障模型進行測試，而冗餘型電路也無法用此模型進行測試，因為依照設計，若只有單一故障，不會因此影響輸出信號。 (zh)
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