About: WDC 65C265

Facets (new session)
Description
Metadata
Settings
- Rule:
- Inverse Functional Properties:
- "Same As":

About: WDC 65C265 Goto Sponge NotDistinct Permalink

An Entity of Type : yago:Wikicat65xxMicroprocessors, within Data Space : dbpedia.demo.openlinksw.com associated with source document(s)
QRcode icon

http://dbpedia.demo.openlinksw.com/describe/?url=http%3A%2F%2Fdbpedia.org%2Fresource%2FWDC_65C265&invfp=IFP_OFF&sas=SAME_AS_OFF

The Western Design Center (WDC) W65C265S is a 16-bit CMOS microcontroller based on a W65C816S processor core, which is a superset of the MOS Technology 6502 processor. The W65C265S consists of a fully static W65C816S CPU core, 8 KB of ROM containing a machine language monitor, 576 bytes of SRAM, a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power feature

Attributes	Values
rdf:type	Thing yago:Artifact100021939 yago:Chip103020034 yago:Conductor103088707 yago:Device103183080 yago:Instrumentality103575240 yago:Microprocessor103760310 yago:Object100002684 yago:PhysicalEntity100001930 yago:SemiconductorDevice104171831 yago:Whole100003553 yago:Wikicat65xxMicroprocessors
rdfs:label	WDC 65C265 (en)
rdfs:comment	The Western Design Center (WDC) W65C265S is a 16-bit CMOS microcontroller based on a W65C816S processor core, which is a superset of the MOS Technology 6502 processor. The W65C265S consists of a fully static W65C816S CPU core, 8 KB of ROM containing a machine language monitor, 576 bytes of SRAM, a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power feature (en)
rdfs:seeAlso	MOS Technology 6502
foaf:depiction
dcterms:subject	16-bit microprocessors 65xx microprocessors
Wikipage page ID	3995814 (xsd:integer)
Wikipage revision ID	1027442378 (xsd:integer)
Link from a Wikipage to another Wikipage	16-bit microprocessors MOS Technology 6502 Static random-access memory Bytes Central Processing Unit WDC 65C02 WDC 65C816 Western Design Center Ambient temperature Kilobyte Microcontroller 65xx microprocessors Megabyte Watchdog timer WDC 65C134 Universal asynchronous receiver-transmitter Machine language monitor Parallel bus Processor cache Read Only Memory
Link from a Wikipage to an external page	http://www.westerndesigncenter.com/Wdc/documentation/265monrom.pdf http://www.westerndesigncenter.com/wdc/documentation/w65c265s.pdf http://www.westerndesigncenter.com/wdc/w65c265s-chip.cfm
sameAs	WDC 65C265 WDC 65C265 WDC 65C265 WDC 65C265
dbp:wikiPageUsesTemplate	dbt:Reflist dbt:See_also dbt:MOS_CPU dbt:Compu-hardware-stub
thumbnail	wiki-commons:Special:FilePath/W65C265S8PL-8_lg.jpg?width=300
has abstract	The Western Design Center (WDC) W65C265S is a 16-bit CMOS microcontroller based on a W65C816S processor core, which is a superset of the MOS Technology 6502 processor. The W65C265S consists of a fully static W65C816S CPU core, 8 KB of ROM containing a machine language monitor, 576 bytes of SRAM, a processor cache under software control, eight 16-bit timers with maskable interrupts, an interrupt-driven parallel bus (PIB), four universal asynchronous receiver-transmitters (UARTs), a watchdog timer that fires a restart interrupt, twenty-nine priority encoded interrupts, a time-of-day clock, two sound generators, a bus control register (BCR) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features. (en)
prov:wasDerivedFrom	wikipedia-en:WDC_65C265?oldid=1027442378&ns=0
page length (characters) of wiki page	2394 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:WDC_65C265
is Link from a Wikipage to another Wikipage of	Mensch Computer Western Design Center WDC 65C134
is foaf:primaryTopic of	wikipedia-en:WDC_65C265

Faceted Search & Find service v1.17_git139 as of Feb 29 2024

Alternative Linked Data Documents: ODE Content Formats:

RDF

ODATA

Microdata

About

OpenLink Virtuoso version 08.03.3330 as of Mar 19 2024, on Linux (x86_64-generic-linux-glibc212), Single-Server Edition (378 GB total memory, 67 GB memory in use)
Data on this page belongs to its respective rights holders.
Virtuoso Faceted Browser Copyright © 2009-2024 OpenLink Software