The ZX8301 is an Uncommitted Logic Array (ULA) integrated circuit designed for the Sinclair QL microcomputer. Also known as the "Master Chip", it provides a Video Display Generator, the division of a 15 MHz crystal to provide the 7.5 MHz system clock, ZX8302 register address decoder, DRAM refresh and bus controller. The ZX8301 is IC22 on the QL motherboard. The ZX8301, when subsequently used in the International Computers Limited (ICL) One Per Desk featured hardware buffering, and the chip proved to be much more reliable in this configuration.
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| - O ZX8301 foi um circuito integrado (ULA) projetado para o microcomputador Sinclair QL. Também conhecido como "Master Chip", era responsável pela geração do sinal de vídeo, clock do sistema em 7,5 MHz (através da divisão por dois de um cristal de 15 MHz), decodificador do registrador de endereços ZX8302, atualização da DRAM e controlador de barramento. O ZX8301 era o CI 22 na placa-mãe do QL. (pt)
- The ZX8301 is an Uncommitted Logic Array (ULA) integrated circuit designed for the Sinclair QL microcomputer. Also known as the "Master Chip", it provides a Video Display Generator, the division of a 15 MHz crystal to provide the 7.5 MHz system clock, ZX8302 register address decoder, DRAM refresh and bus controller. The ZX8301 is IC22 on the QL motherboard. The ZX8301, when subsequently used in the International Computers Limited (ICL) One Per Desk featured hardware buffering, and the chip proved to be much more reliable in this configuration. (en)
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| - The ZX8301 is an Uncommitted Logic Array (ULA) integrated circuit designed for the Sinclair QL microcomputer. Also known as the "Master Chip", it provides a Video Display Generator, the division of a 15 MHz crystal to provide the 7.5 MHz system clock, ZX8302 register address decoder, DRAM refresh and bus controller. The ZX8301 is IC22 on the QL motherboard. The Sinclair Research business model had always been to work toward a maximum performance to price ratio (as was evidenced by the keyboard mechanisms in the QL and earlier Sinclair models). Unfortunately this focus on price and performance often resulted in cost cutting in the design and build of Sinclair's machines. One such cost driven decision (failing to use a hardware buffer integrated circuit (IC) between the IC pins and the external RGB monitor connection) caused the ZX8301 to quickly develop a reputation for being fragile and easy to damage, particularly if the monitor plug was inserted or removed while the QL was powered up. Such an action resulted in damage to the video circuitry and almost always required replacement of the ZX8301. The ZX8301, when subsequently used in the International Computers Limited (ICL) One Per Desk featured hardware buffering, and the chip proved to be much more reliable in this configuration. (en)
- O ZX8301 foi um circuito integrado (ULA) projetado para o microcomputador Sinclair QL. Também conhecido como "Master Chip", era responsável pela geração do sinal de vídeo, clock do sistema em 7,5 MHz (através da divisão por dois de um cristal de 15 MHz), decodificador do registrador de endereços ZX8302, atualização da DRAM e controlador de barramento. O ZX8301 era o CI 22 na placa-mãe do QL. (pt)
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