About: VHDL-AMS

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VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999). The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.

Attributes	Values
rdf:type	chemical substance yago:WikicatComputerLanguages yago:Abstraction100002137 yago:ArtificialLanguage106894544 yago:Communication100033020 yago:ComputerLanguage106899633 yago:Language106282651 yago:ProgrammingLanguage106898352 yago:WikicatHardwareDescriptionLanguages
rdfs:label	VHDL-AMS (fr) VHDL-AMS (en) VHDL-AMS (zh)
rdfs:comment	VHDL-AMS 是硬件描述语言VHDL（IEEE 1076-1993）的一个衍生部分。它包含了模拟和混合信号的扩展，从而能够对模拟和混合信号系统的行为进行描述。 (zh) VHDL-AMS est un dérivé du langage de description matériel VHDL (norme IEEE 1076-1993). Il comprend des extensions analogiques et des signaux mixtes (en anglais analog and mixed-signal, AMS) afin de définir le comportement des systèmes à signaux analogiques et mixtes (IEEE 1076.1-1999). Il est important de noter que le VHDL-AMS ne constitue pas un langage de conception ou synthèse. Il s'agit seulement d'un langage de description du matériel. (fr) VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999). The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components. (en)
dct:subject	Hardware description languages
Wikipage page ID	14453419 (xsd:integer)
Wikipage revision ID	1074741949 (xsd:integer)
Link from a Wikipage to another Wikipage	Cadence Design Systems Electronic design automation VHDL Verilog Verilog-AMS Mentor Graphics Very-large-scale integration Dolphin Integration ANSYS Diode VHSIC hardware description language Radio frequency Hardware description language Hardware description languages Synopsys Modelica
sameAs	VHDL-AMS VHDL-AMS VHDL-AMS VHDL-AMS VHDL-AMS VHDL-AMS VHDL-AMS VHDL-AMS
dbp:wikiPageUsesTemplate	dbt:Reflist dbt:Short_description dbt:Use_American_English dbt:Programmable_Logic
has abstract	VHDL-AMS est un dérivé du langage de description matériel VHDL (norme IEEE 1076-1993). Il comprend des extensions analogiques et des signaux mixtes (en anglais analog and mixed-signal, AMS) afin de définir le comportement des systèmes à signaux analogiques et mixtes (IEEE 1076.1-1999). La norme VHDL-AMS a été instaurée dans l'intention de permettre aux concepteurs de systèmes à signaux analogiques et mixtes et de circuits intégrés de pouvoir créer et d'utiliser des modules qui encapsulent les descriptions de comportement de haut niveau, aussi bien que des descriptions structurelles de systèmes et de composants. VHDL-AMS définit un langage de modélisation standardisé par l'industrie pour les circuits à signaux mixtes. Il fournit à la fois le temps-continu et les sémantiques de modélisation d'événements. Il est donc approprié pour les circuits analogiques, numériques et mixtes. Il est particulièrement bien adapté pour la vérification de circuits intégrés complexes qui allient des signaux analogiques, mixtes et des fréquences radios. Il est important de noter que le VHDL-AMS ne constitue pas un langage de conception ou synthèse. Il s'agit seulement d'un langage de description du matériel. (fr) VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999). The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components. VHDL-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and radio frequency integrated circuits. (en) VHDL-AMS 是硬件描述语言VHDL（IEEE 1076-1993）的一个衍生部分。它包含了模拟和混合信号的扩展，从而能够对模拟和混合信号系统的行为进行描述。 (zh)
gold:hypernym	Derivative
prov:wasDerivedFrom	wikipedia-en:VHDL-AMS?oldid=1074741949&ns=0
page length (characters) of wiki page	2824 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:VHDL-AMS
is Link from a Wikipage to another Wikipage of	Behavioral modeling in computer-aided design Electrical network Electronic circuit simulation VHDL Design Automation Standards Committee Verilog-AMS List of programming languages by type Analog verification Flow to HDL Ken Kundert Mixed-signal integrated circuit AMS Hardware description language Code refactoring Saber (software)
is Wikipage disambiguates of	AMS
is dialects of	VHDL
is foaf:primaryTopic of	wikipedia-en:VHDL-AMS

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