The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture [1] Archived 2017-01-15 at the Wayback Machine. A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken over by the Free and Open Source Silicon Foundation at the librecores.org website. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).