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Statements

Subject Item
dbr:EnCore_Processor
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yago:WikicatMicroprocessors yago:Device103183080 yago:Object100002684 yago:Microprocessor103760310 yago:SemiconductorDevice104171831 yago:Conductor103088707 yago:Artifact100021939 yago:Instrumentality103575240 yago:PhysicalEntity100001930 yago:Whole100003553 yago:Chip103020034 dbo:Software
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EnCore Processor
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The EnCore microprocessor family is a configurable and extendable implementation of a compact 32-bit RISC instruction set architecture - developed by the PASTA Research Group at the University of Edinburgh School of Informatics. The following are key features of the EnCore microprocessor family: All of the EnCore test chips are named after hills in Edinburgh; Calton, being the smallest, is the first of these. The second, Castle, is named after the rock on which Edinburgh Castle is built.
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The EnCore microprocessor family is a configurable and extendable implementation of a compact 32-bit RISC instruction set architecture - developed by the PASTA Research Group at the University of Edinburgh School of Informatics. The following are key features of the EnCore microprocessor family: * 5 stage pipeline * highest operating frequency in its class * lowest possible dynamic energy consumption - 99% of flip-flops automatically clock-gated using typical synthesis tools * most non-memory operations achieving single-cycle latency, and no more than one load-delay slot * easy configurability of cache architectures * compact baseline instruction set architecture (ISA), including freely-mixed 16-bit and 32-bit encodings for maximum code density * no overhead for switching between 16- and 32-bit instruction encodings All of the EnCore test chips are named after hills in Edinburgh; Calton, being the smallest, is the first of these. The second, Castle, is named after the rock on which Edinburgh Castle is built.
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