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Statements

Subject Item
dbr:Latency_oriented_processor_architecture
rdfs:label
Latency oriented processor architecture
rdfs:comment
Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on.
dct:subject
dbc:Microprocessors
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51623894
dbo:wikiPageRevisionID
1123640389
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dbr:Execution_unit dbr:Single_instruction,_single_data dbr:Reservation_station dbr:Instructions_per_cycle dbr:MMX_(instruction_set) dbr:Thread_(computing) dbr:Temporal_locality dbr:CPU_cache dbr:Write_after_read dbr:Graphics_processing_unit dbc:Microprocessors dbr:Latency_(engineering) dbr:Operand_forwarding dbr:Hazard_(computer_architecture) dbr:Non-volatile_storage dbr:Memory_access_time dbr:Cache_(computing) dbr:Data_dependency dbr:Throughput dbr:Microprocessor dbr:Single_instruction,_multiple_data dbr:Re-order_buffer dbr:Random-access_memory dbr:Streaming_SIMD_Extensions dbr:Reduced_instruction_set_computing dbr:Main_memory dbr:Microarchitecture dbr:Pipeline_(computing) dbr:Instruction_level_parallelism n14:store_architecture dbr:Locality_of_reference dbr:Central_processing_unit
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dbo:abstract
Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on.
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wikipedia-en:Latency_oriented_processor_architecture?oldid=1123640389&ns=0
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12933
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wikipedia-en:Latency_oriented_processor_architecture