. "R10000 \u306F\u3001MIPS IV\u547D\u4EE4\u30BB\u30C3\u30C8\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3 (ISA) \u3092\u5B9F\u88C5\u3057\u305FRISC\u30DE\u30A4\u30AF\u30ED\u30D7\u30ED\u30BB\u30C3\u30B5\u3067\u3001\u5F53\u6642\u30B7\u30EA\u30B3\u30F3\u30B0\u30E9\u30D5\u30A3\u30C3\u30AF\u30B9 (SGI) \u306E\u5B50\u4F1A\u793E\u3068\u306A\u3063\u3066\u3044\u305F\u30DF\u30C3\u30D7\u30B9\u30FB\u30C6\u30AF\u30CE\u30ED\u30B8\u30FC\u30BA (MTI) \u304C\u958B\u767A\u3057\u305F\u3002\u958B\u767A\u30B3\u30FC\u30C9\u540D\u306F \"T5\"\u3002\u30C1\u30FC\u30D5\u30C7\u30B6\u30A4\u30CA\u30FC\u306F Chris Rowen \u3068 Kenneth C. Yeager\u3002R10000\u306E\u30DE\u30A4\u30AF\u30ED\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u306F ANDES\uFF08Architecture with Non-sequential Dynamic Execution Scheduling\u3001\u975E\u9010\u6B21\u7684\u52D5\u7684\u5B9F\u884C\u30B9\u30B1\u30B8\u30E5\u30FC\u30EA\u30F3\u30B0\u30FB\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\uFF09\u3068\u540D\u4ED8\u3051\u3089\u308C\u3066\u3044\u308B\u3002\u30CF\u30A4\u30A8\u30F3\u30C9\u3067\u306FR8000\u3001\u305D\u308C\u4EE5\u5916\u3067\u306FR4400\u306E\u5F8C\u7D99\u3068\u3057\u3066\u3001\u305D\u308C\u3089\u306B\u53D6\u3063\u3066\u4EE3\u308F\u3063\u305F\u3002MTI\u306F\u30D5\u30A1\u30D6\u30EC\u30B9\u4F01\u696D\u3067\u3042\u308A\u3001\u5B9F\u969B\u306E\u88FD\u9020\u306F\u65E5\u672C\u96FB\u6C17 (NEC) \u3068\u6771\u829D\u304C\u884C\u3063\u305F\u3002R4000/R4400\u4EE5\u4E0A\u306B\u8A2D\u5099\u6295\u8CC7\u304C\u304B\u304B\u308B\u305F\u3081\u3001\u305D\u308C\u307E\u3067MIPS\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u306E\u30DE\u30A4\u30AF\u30ED\u30D7\u30ED\u30BB\u30C3\u30B5\u3092\u624B\u304C\u3051\u3066\u3044\u305FIDT\u306A\u3069\u306E\u534A\u5C0E\u4F53\u4F01\u696D\u306FR10000\u3092\u88FD\u9020\u3057\u306A\u304B\u3063\u305F\u3002"@ja . . . . . . . . . . . . . . . "yes"@en . . . . . "20048"^^ . . . . . . . "En 1995, MIPS a lanc\u00E9 le processeur R10000. Ce processeur sous forme d'une seule puce fonctionne \u00E0 une fr\u00E9quence plus \u00E9lev\u00E9e que le R8000, et poss\u00E8de des caches d'instructions et de donn\u00E9es plus grands (32 Ko). C'est un processeur super-scalaire mais son innovation majeure r\u00E9side dans l'ex\u00E9cution dans le d\u00E9sordre (out-of-order execution). M\u00EAme avec pipeline m\u00E9moire unique et une unit\u00E9 de traitement des flottants (FPU) simple, l'am\u00E9lioration de l'unit\u00E9 de traitement des entiers, le faible co\u00FBt et une densit\u00E9 \u00E9lev\u00E9e ont fait du R10000 un processeur tr\u00E8s int\u00E9ressant. \n* Portail de l\u2019\u00E9lectricit\u00E9 et de l\u2019\u00E9lectronique \n* Portail de l\u2019informatique"@fr . "R10000"@ja . . . "R10000 \u306F\u3001MIPS IV\u547D\u4EE4\u30BB\u30C3\u30C8\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3 (ISA) \u3092\u5B9F\u88C5\u3057\u305FRISC\u30DE\u30A4\u30AF\u30ED\u30D7\u30ED\u30BB\u30C3\u30B5\u3067\u3001\u5F53\u6642\u30B7\u30EA\u30B3\u30F3\u30B0\u30E9\u30D5\u30A3\u30C3\u30AF\u30B9 (SGI) \u306E\u5B50\u4F1A\u793E\u3068\u306A\u3063\u3066\u3044\u305F\u30DF\u30C3\u30D7\u30B9\u30FB\u30C6\u30AF\u30CE\u30ED\u30B8\u30FC\u30BA (MTI) \u304C\u958B\u767A\u3057\u305F\u3002\u958B\u767A\u30B3\u30FC\u30C9\u540D\u306F \"T5\"\u3002\u30C1\u30FC\u30D5\u30C7\u30B6\u30A4\u30CA\u30FC\u306F Chris Rowen \u3068 Kenneth C. Yeager\u3002R10000\u306E\u30DE\u30A4\u30AF\u30ED\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u306F ANDES\uFF08Architecture with Non-sequential Dynamic Execution Scheduling\u3001\u975E\u9010\u6B21\u7684\u52D5\u7684\u5B9F\u884C\u30B9\u30B1\u30B8\u30E5\u30FC\u30EA\u30F3\u30B0\u30FB\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\uFF09\u3068\u540D\u4ED8\u3051\u3089\u308C\u3066\u3044\u308B\u3002\u30CF\u30A4\u30A8\u30F3\u30C9\u3067\u306FR8000\u3001\u305D\u308C\u4EE5\u5916\u3067\u306FR4400\u306E\u5F8C\u7D99\u3068\u3057\u3066\u3001\u305D\u308C\u3089\u306B\u53D6\u3063\u3066\u4EE3\u308F\u3063\u305F\u3002MTI\u306F\u30D5\u30A1\u30D6\u30EC\u30B9\u4F01\u696D\u3067\u3042\u308A\u3001\u5B9F\u969B\u306E\u88FD\u9020\u306F\u65E5\u672C\u96FB\u6C17 (NEC) \u3068\u6771\u829D\u304C\u884C\u3063\u305F\u3002R4000/R4400\u4EE5\u4E0A\u306B\u8A2D\u5099\u6295\u8CC7\u304C\u304B\u304B\u308B\u305F\u3081\u3001\u305D\u308C\u307E\u3067MIPS\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u306E\u30DE\u30A4\u30AF\u30ED\u30D7\u30ED\u30BB\u30C3\u30B5\u3092\u624B\u304C\u3051\u3066\u3044\u305FIDT\u306A\u3069\u306E\u534A\u5C0E\u4F53\u4F01\u696D\u306FR10000\u3092\u88FD\u9020\u3057\u306A\u304B\u3063\u305F\u3002"@ja . . . . . . . . . . . . . "R10000"@es . "The R10000, code-named \"T5\", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400."@en . . . . . . . . . . . . . . . . . . . . . . . "4047822"^^ . . . . . . . . . . . . . "R10000 (\u043A\u043E\u0434\u043E\u0432\u043E\u0435 \u0438\u043C\u044F \u00AB\u04225\u00BB) \u2014 RISC-\u043C\u0438\u043A\u0440\u043E\u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440, \u0440\u0435\u0430\u043B\u0438\u0437\u0443\u044E\u0449\u0438\u0439 \u043D\u0430\u0431\u043E\u0440 \u0438\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0438\u0439 MIPS IV. \u0420\u0430\u0437\u0440\u0430\u0431\u043E\u0442\u0430\u043D \u043A\u043E\u043C\u043F\u0430\u043D\u0438\u0435\u0439 MIPS Technoligies, Inc. (MTI, \u043F\u043E\u0437\u0436\u0435 \u0441\u0442\u0430\u0432\u0448\u0435\u0439 \u043F\u043E\u0434\u0440\u0430\u0437\u0434\u0435\u043B\u0435\u043D\u0438\u0435\u043C SGI). \u0413\u043B\u0430\u0432\u043D\u044B\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043E\u0442\u0447\u0438\u043A\u0438 \u2014 \u041A\u0440\u0438\u0441 \u0420\u043E\u0443\u044D\u043D \u0438 \u041A\u0435\u043D\u043D\u0435\u0442 \u0421. \u0419\u0435\u0433\u0435\u0440. R10000 \u043F\u043E\u0441\u0442\u0440\u043E\u0435\u043D \u043D\u0430 \u043E\u0441\u043D\u043E\u0432\u0435 \u043C\u0438\u043A\u0440\u043E\u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u044B ANDES (Architecture with Non-sequential Dynamic Execution Scheduling \u2014 \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u0430 \u0441 \u043D\u0435\u043F\u043E\u0441\u043B\u0435\u0434\u043E\u0432\u0430\u0442\u0435\u043B\u044C\u043D\u044B\u043C \u0434\u0438\u043D\u0430\u043C\u0438\u0447\u0435\u0441\u043A\u0438\u043C \u043F\u043B\u0430\u043D\u0438\u0440\u043E\u0432\u0430\u043D\u0438\u0435\u043C \u0438\u0441\u043F\u043E\u043B\u043D\u0435\u043D\u0438\u044F). R10000 \u0432\u043E \u043C\u043D\u043E\u0433\u043E\u043C \u0437\u0430\u043C\u0435\u043D\u0438\u043B R8000 \u0432 \u0432\u044B\u0441\u043E\u043A\u043E\u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u0442\u0435\u043B\u044C\u043D\u043E\u043C \u0441\u0435\u0433\u043C\u0435\u043D\u0442\u0435 \u0438 \u0432 \u0434\u0440\u0443\u0433\u0438\u0445 \u043F\u0440\u0438\u043C\u0435\u043D\u0435\u043D\u0438\u044F\u0445. MTI \u044F\u0432\u043B\u044F\u0435\u0442\u0441\u044F \u0431\u0435\u0441\u0444\u0430\u0431\u0440\u0438\u0447\u043D\u043E\u0439 \u043A\u043E\u043C\u043F\u0430\u043D\u0438\u0435\u0439, \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u044B R10000 \u0438\u0437\u0433\u043E\u0442\u0430\u0432\u043B\u0438\u0432\u0430\u043B\u0438\u0441\u044C NEC \u0438 Toshiba. \u041F\u0440\u0435\u0434\u044B\u0434\u0443\u0449\u0438\u0435 \u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u0442\u0435\u043B\u0438 \u043C\u0438\u043A\u0440\u043E\u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 MIPS, IDT \u0438 \u0434\u0440\u0443\u0433\u0438\u0435 \u043D\u0435 \u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u043B\u0438 R10000, \u0442\u0430\u043A \u043A\u0430\u043A \u044D\u0442\u043E \u0431\u044B\u043B\u043E \u0431\u043E\u043B\u0435\u0435 \u0434\u043E\u0440\u043E\u0433\u0438\u043C, \u0447\u0435\u043C R4000 \u0438 R4400."@ru . . . . . . . . . "R10000 (\u043A\u043E\u0434\u043E\u0432\u043E\u0435 \u0438\u043C\u044F \u00AB\u04225\u00BB) \u2014 RISC-\u043C\u0438\u043A\u0440\u043E\u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440, \u0440\u0435\u0430\u043B\u0438\u0437\u0443\u044E\u0449\u0438\u0439 \u043D\u0430\u0431\u043E\u0440 \u0438\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0438\u0439 MIPS IV. \u0420\u0430\u0437\u0440\u0430\u0431\u043E\u0442\u0430\u043D \u043A\u043E\u043C\u043F\u0430\u043D\u0438\u0435\u0439 MIPS Technoligies, Inc. (MTI, \u043F\u043E\u0437\u0436\u0435 \u0441\u0442\u0430\u0432\u0448\u0435\u0439 \u043F\u043E\u0434\u0440\u0430\u0437\u0434\u0435\u043B\u0435\u043D\u0438\u0435\u043C SGI). \u0413\u043B\u0430\u0432\u043D\u044B\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043E\u0442\u0447\u0438\u043A\u0438 \u2014 \u041A\u0440\u0438\u0441 \u0420\u043E\u0443\u044D\u043D \u0438 \u041A\u0435\u043D\u043D\u0435\u0442 \u0421. \u0419\u0435\u0433\u0435\u0440. R10000 \u043F\u043E\u0441\u0442\u0440\u043E\u0435\u043D \u043D\u0430 \u043E\u0441\u043D\u043E\u0432\u0435 \u043C\u0438\u043A\u0440\u043E\u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u044B ANDES (Architecture with Non-sequential Dynamic Execution Scheduling \u2014 \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u0430 \u0441 \u043D\u0435\u043F\u043E\u0441\u043B\u0435\u0434\u043E\u0432\u0430\u0442\u0435\u043B\u044C\u043D\u044B\u043C \u0434\u0438\u043D\u0430\u043C\u0438\u0447\u0435\u0441\u043A\u0438\u043C \u043F\u043B\u0430\u043D\u0438\u0440\u043E\u0432\u0430\u043D\u0438\u0435\u043C \u0438\u0441\u043F\u043E\u043B\u043D\u0435\u043D\u0438\u044F). R10000 \u0432\u043E \u043C\u043D\u043E\u0433\u043E\u043C \u0437\u0430\u043C\u0435\u043D\u0438\u043B R8000 \u0432 \u0432\u044B\u0441\u043E\u043A\u043E\u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u0442\u0435\u043B\u044C\u043D\u043E\u043C \u0441\u0435\u0433\u043C\u0435\u043D\u0442\u0435 \u0438 \u0432 \u0434\u0440\u0443\u0433\u0438\u0445 \u043F\u0440\u0438\u043C\u0435\u043D\u0435\u043D\u0438\u044F\u0445. MTI \u044F\u0432\u043B\u044F\u0435\u0442\u0441\u044F \u0431\u0435\u0441\u0444\u0430\u0431\u0440\u0438\u0447\u043D\u043E\u0439 \u043A\u043E\u043C\u043F\u0430\u043D\u0438\u0435\u0439, \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u044B R10000 \u0438\u0437\u0433\u043E\u0442\u0430\u0432\u043B\u0438\u0432\u0430\u043B\u0438\u0441\u044C NEC \u0438 Toshiba. \u041F\u0440\u0435\u0434\u044B\u0434\u0443\u0449\u0438\u0435 \u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u0442\u0435\u043B\u0438 \u043C\u0438\u043A\u0440\u043E\u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 MIPS, IDT \u0438 \u0434\u0440\u0443\u0433\u0438\u0435 \u043D\u0435 \u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u043B\u0438 R10000, \u0442\u0430\u043A \u043A\u0430\u043A \u044D\u0442\u043E \u0431\u044B\u043B\u043E \u0431\u043E\u043B\u0435\u0435 \u0434\u043E\u0440\u043E\u0433\u0438\u043C, \u0447\u0435\u043C R4000 \u0438 R4400."@ru . . "The R10000, code-named \"T5\", is a RISC microprocessor implementation of the MIPS IV instruction set architecture (ISA) developed by MIPS Technologies, Inc. (MTI), then a division of Silicon Graphics, Inc. (SGI). The chief designers are Chris Rowen and Kenneth C. Yeager. The R10000 microarchitecture is known as ANDES, an abbreviation for Architecture with Non-sequential Dynamic Execution Scheduling. The R10000 largely replaces the R8000 in the high-end and the R4400 elsewhere. MTI was a fabless semiconductor company; the R10000 was fabricated by NEC and Toshiba. Previous fabricators of MIPS microprocessors such as Integrated Device Technology (IDT) and three others did not fabricate the R10000 as it was more expensive to do so than the R4000 and R4400."@en . . . . . . . . . "R10000"@en . . . . . . . "R10000"@ru . . . . . . . . . . . "September 2018"@en . . . . . . . . . "InternetArchiveBot"@en . . . . . . . . . "1061339740"^^ . . "R10000"@fr . "En 1995, MIPS a lanc\u00E9 le processeur R10000. Ce processeur sous forme d'une seule puce fonctionne \u00E0 une fr\u00E9quence plus \u00E9lev\u00E9e que le R8000, et poss\u00E8de des caches d'instructions et de donn\u00E9es plus grands (32 Ko). C'est un processeur super-scalaire mais son innovation majeure r\u00E9side dans l'ex\u00E9cution dans le d\u00E9sordre (out-of-order execution). M\u00EAme avec pipeline m\u00E9moire unique et une unit\u00E9 de traitement des flottants (FPU) simple, l'am\u00E9lioration de l'unit\u00E9 de traitement des entiers, le faible co\u00FBt et une densit\u00E9 \u00E9lev\u00E9e ont fait du R10000 un processeur tr\u00E8s int\u00E9ressant."@fr . . . . . . .