. "Southbridge (ji\u017En\u00ED m\u016Fstek) je tak\u00E9 zn\u00E1m jako vstupn\u011B-v\u00FDstupn\u00ED \u0159adi\u010D (I/O Controller Hub). \u010Cip realizuje pomalej\u0161\u00ED funkce z\u00E1kladn\u00ED desky v po\u010D\u00EDta\u010Dov\u00E9 architektu\u0159e se severn\u00EDm a ji\u017En\u00EDm m\u016Fstkem. Ji\u017En\u00ED m\u016Fstek odli\u0161\u00EDme od severn\u00EDho snadno tak, \u017Ee nen\u00ED p\u0159\u00EDmo spojen s procesorem. Severn\u00ED m\u016Fstek realizuje spojen\u00ED ji\u017En\u00EDho m\u016Fstku a procesoru."@cs . . . . . . . "October 2018"@en . . "\u5357\u6865\uFF08\u82F1\u8A9E\uFF1ASouthbridge\uFF09\u662F\u57FA\u4E8E\u4E2A\u4EBA\u7535\u8111\u4E3B\u677F\u82AF\u7247\u7EC4\u67B6\u69CB\u4E2D\u7684\u5176\u4E2D\u4E00\u679A\u82AF\u7247\u3002\u5357\u6865\u8BBE\u8BA1\u7528\u6765\u5904\u7406\u4F4E\u901F\u4FE1\u53F7\uFF0C\u901A\u8FC7\u5317\u6865\u4E0E\u4E2D\u592E\u8655\u7406\u5668\u8054\u7CFB\u3002\u5404\u6676\u7247\u7D44\u5EE0\u5546\u7684\u5357\u6865\u540D\u7A31\u90FD\u6709\u6240\u4E0D\u540C\uFF0C\u4F8B\u5982\u82F1\u7279\u723E\u7A31\u4E4B\u70BAI/O\u8DEF\u5F91\u63A7\u5236\u5668\uFF08ICH\uFF09\u6216\u5E73\u53F0\u8DEF\u5F91\u63A7\u5236\u5668\uFF08PCH\uFF09\uFF0CNVIDIA\u7684\u7A31\u70BAMCP\uFF0CATI\u7684\u7A31\u70BAIXP/SB\uFF0CAMD\u7528FCH\uFF08Fusion Control Hub\uFF09\u4EE3\u8868AMD APU/AMD Ryzen/AMD EPYC\u7684\u5357\u6A4B\u6676\u7247\u3002 \u5357\u6A4B\u5305\u542B\u5927\u591A\u6578\u5468\u908A\u8A2D\u5099\u4ECB\u9762\u3001\u591A\u5A92\u9AD4\u63A7\u5236\u5668\u548C\u901A\u8A0A\u4ECB\u9762\u529F\u80FD\u3002\u4F8B\u5982PCI/\u4F4E\u901FPCIe\uFF08\u5982PCIe x1\uFF09\u63A7\u5236\u5668\u3001ATA/SATA\u63A7\u5236\u5668\u3001USB\u63A7\u5236\u5668\u3001\u7DB2\u8DEF\u63A7\u5236\u5668\u3001\u97F3\u6548\u63A7\u5236\u5668\u3002 \u4E2D\u9AD8\u968E\u7684\u5357\u6A4B\u53EF\u4EE5\u63D0\u4F9B\u300CFake RAID\u300D\u529F\u80FD\u3002\u82F1\u7279\u723E\u7684ICHxR\u7CFB\u5217\u5357\u6A4B\u652F\u63F4\u82F1\u7279\u5C14\u5FEB\u901F\u5B58\u50A8\u6280\u672F\u3002"@zh . . . . . "\u042E\u0436\u043D\u044B\u0439 \u043C\u043E\u0441\u0442 (\u0430\u043D\u0433\u043B. Southbridge) \u2014 \u0444\u0443\u043D\u043A\u0446\u0438\u043E\u043D\u0430\u043B\u044C\u043D\u044B\u0439 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440, \u0442\u0430\u043A\u0436\u0435 \u0438\u0437\u0432\u0435\u0441\u0442\u0435\u043D \u043A\u0430\u043A \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440-\u043A\u043E\u043D\u0446\u0435\u043D\u0442\u0440\u0430\u0442\u043E\u0440 \u0432\u0432\u043E\u0434\u0430-\u0432\u044B\u0432\u043E\u0434\u0430 (\u043E\u0442 \u0430\u043D\u0433\u043B. I/O Controller Hub, ICH). \u041E\u0431\u044B\u0447\u043D\u043E \u044D\u0442\u043E \u043E\u0434\u043D\u0430 \u043C\u0438\u043A\u0440\u043E\u0441\u0445\u0435\u043C\u0430, \u043A\u043E\u0442\u043E\u0440\u0430\u044F \u0441\u0432\u044F\u0437\u044B\u0432\u0430\u0435\u0442 \u00AB\u043C\u0435\u0434\u043B\u0435\u043D\u043D\u044B\u0435\u00BB (\u043F\u043E \u0441\u0440\u0430\u0432\u043D\u0435\u043D\u0438\u044E \u0441\u043E \u0441\u0432\u044F\u0437\u043A\u043E\u0439 \u00AB\u0426\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u044B\u0439 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440-\u041E\u0417\u0423\u00BB) \u0432\u0437\u0430\u0438\u043C\u043E\u0434\u0435\u0439\u0441\u0442\u0432\u0438\u044F (\u043D\u0430\u043F\u0440\u0438\u043C\u0435\u0440, Low Pin Count, Super I/O \u0438\u043B\u0438 \u0440\u0430\u0437\u044A\u0451\u043C\u044B \u0448\u0438\u043D \u0434\u043B\u044F \u043F\u043E\u0434\u043A\u043B\u044E\u0447\u0435\u043D\u0438\u044F \u043F\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0439\u043D\u044B\u0445 \u0443\u0441\u0442\u0440\u043E\u0439\u0441\u0442\u0432) \u043D\u0430 \u043C\u0430\u0442\u0435\u0440\u0438\u043D\u0441\u043A\u043E\u0439 \u043F\u043B\u0430\u0442\u0435 \u0441 \u0426\u041F\u0423 \u0447\u0435\u0440\u0435\u0437 \u0441\u0435\u0432\u0435\u0440\u043D\u044B\u0439 \u043C\u043E\u0441\u0442, \u043A\u043E\u0442\u043E\u0440\u044B\u0439 \u043E\u0431\u044B\u0447\u043D\u043E \u043F\u043E\u0434\u043A\u043B\u044E\u0447\u0451\u043D \u043D\u0430\u043F\u0440\u044F\u043C\u0443\u044E \u043A \u0446\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u043E\u043C\u0443 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0443 \u043A\u043E\u043C\u043F\u044C\u044E\u0442\u0435\u0440\u0430."@ru . . . "El Southbridge o puente sur, tambi\u00E9n conocido como Concentrador de Controladores de Entrada/Salida (I/O Controller Hub, ICH), es un circuito integrado que se encarga de coordinar los diferentes dispositivos de entrada y salida y algunas otras funcionalidades de baja velocidad dentro de la tarjeta madre. El southbridge no est\u00E1 conectado a la CPU y se comunica con ella indirectamente a trav\u00E9s del northbridge - Puente Norte. La funcionalidad encontrada en los southbridges actuales incluye soporte para: ejemplos:"@es . . . . . . "Mostek po\u0142udniowy (ang. southbridge) \u2013 element wsp\u00F3\u0142czesnych chipset\u00F3w, realizuj\u0105cy po\u0142\u0105czenie procesora do wolniejszej cz\u0119\u015Bci wyposa\u017Cenia mikrokomputera: \n* nap\u0119d\u00F3w dysk\u00F3w twardych (z\u0142\u0105cza IDE/ATA/SATA/ATAPI) \n* magistral ISA, PCI \n* sterownika przerwa\u0144 \n* sterownika DMA \n* nieulotnej pami\u0119ci BIOS \n* modu\u0142u zegara czasu rzeczywistego Opcjonalnie mostek po\u0142udniowy mo\u017Ce obs\u0142ugiwa\u0107 r\u00F3wnie\u017C: \n* magistral\u0119 FireWire \n* magistral\u0119 USB \n* z\u0142\u0105cze do sterownika RAID \n* z\u0142\u0105cze Ethernet"@pl . "\u042E\u0436\u043D\u044B\u0439 \u043C\u043E\u0441\u0442 (\u0430\u043D\u0433\u043B. Southbridge) \u2014 \u0444\u0443\u043D\u043A\u0446\u0438\u043E\u043D\u0430\u043B\u044C\u043D\u044B\u0439 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440, \u0442\u0430\u043A\u0436\u0435 \u0438\u0437\u0432\u0435\u0441\u0442\u0435\u043D \u043A\u0430\u043A \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u043B\u0435\u0440-\u043A\u043E\u043D\u0446\u0435\u043D\u0442\u0440\u0430\u0442\u043E\u0440 \u0432\u0432\u043E\u0434\u0430-\u0432\u044B\u0432\u043E\u0434\u0430 (\u043E\u0442 \u0430\u043D\u0433\u043B. I/O Controller Hub, ICH). \u041E\u0431\u044B\u0447\u043D\u043E \u044D\u0442\u043E \u043E\u0434\u043D\u0430 \u043C\u0438\u043A\u0440\u043E\u0441\u0445\u0435\u043C\u0430, \u043A\u043E\u0442\u043E\u0440\u0430\u044F \u0441\u0432\u044F\u0437\u044B\u0432\u0430\u0435\u0442 \u00AB\u043C\u0435\u0434\u043B\u0435\u043D\u043D\u044B\u0435\u00BB (\u043F\u043E \u0441\u0440\u0430\u0432\u043D\u0435\u043D\u0438\u044E \u0441\u043E \u0441\u0432\u044F\u0437\u043A\u043E\u0439 \u00AB\u0426\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u044B\u0439 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440-\u041E\u0417\u0423\u00BB) \u0432\u0437\u0430\u0438\u043C\u043E\u0434\u0435\u0439\u0441\u0442\u0432\u0438\u044F (\u043D\u0430\u043F\u0440\u0438\u043C\u0435\u0440, Low Pin Count, Super I/O \u0438\u043B\u0438 \u0440\u0430\u0437\u044A\u0451\u043C\u044B \u0448\u0438\u043D \u0434\u043B\u044F \u043F\u043E\u0434\u043A\u043B\u044E\u0447\u0435\u043D\u0438\u044F \u043F\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0439\u043D\u044B\u0445 \u0443\u0441\u0442\u0440\u043E\u0439\u0441\u0442\u0432) \u043D\u0430 \u043C\u0430\u0442\u0435\u0440\u0438\u043D\u0441\u043A\u043E\u0439 \u043F\u043B\u0430\u0442\u0435 \u0441 \u0426\u041F\u0423 \u0447\u0435\u0440\u0435\u0437 \u0441\u0435\u0432\u0435\u0440\u043D\u044B\u0439 \u043C\u043E\u0441\u0442, \u043A\u043E\u0442\u043E\u0440\u044B\u0439 \u043E\u0431\u044B\u0447\u043D\u043E \u043F\u043E\u0434\u043A\u043B\u044E\u0447\u0451\u043D \u043D\u0430\u043F\u0440\u044F\u043C\u0443\u044E \u043A \u0446\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u043E\u043C\u0443 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0443 \u043A\u043E\u043C\u043F\u044C\u044E\u0442\u0435\u0440\u0430."@ru . . . "1122974956"^^ . "9310"^^ . . . . "Southbridge"@el . . "SouthBridge \u00E9s la part del joc de xips que controla el sistema d'entrada/eixida de dades, el bus d'IDE i en conseq\u00FC\u00E8ncia, als dispositius d'emmagatzemament, l'\u00E0udio i altres busos, com el Bus s\u00E8rie universal, el ISA, el port s\u00E8rie, el port paral\u00B7lel, etc. El seu nom es deu al fet que la seua localitzaci\u00F3 habitual \u00E9s a la zona sur del conjunt Chipset en la placa mare."@ca . . . "Le southbridge est l\u2019une des deux puces du chipset d\u2019une carte m\u00E8re dont l\u2019autre puce est le northbridge."@fr . "\uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0"@ko . "Sydbrygga"@sv . . . . . . . . "\u5357\u6865\uFF08\u82F1\u8A9E\uFF1ASouthbridge\uFF09\u662F\u57FA\u4E8E\u4E2A\u4EBA\u7535\u8111\u4E3B\u677F\u82AF\u7247\u7EC4\u67B6\u69CB\u4E2D\u7684\u5176\u4E2D\u4E00\u679A\u82AF\u7247\u3002\u5357\u6865\u8BBE\u8BA1\u7528\u6765\u5904\u7406\u4F4E\u901F\u4FE1\u53F7\uFF0C\u901A\u8FC7\u5317\u6865\u4E0E\u4E2D\u592E\u8655\u7406\u5668\u8054\u7CFB\u3002\u5404\u6676\u7247\u7D44\u5EE0\u5546\u7684\u5357\u6865\u540D\u7A31\u90FD\u6709\u6240\u4E0D\u540C\uFF0C\u4F8B\u5982\u82F1\u7279\u723E\u7A31\u4E4B\u70BAI/O\u8DEF\u5F91\u63A7\u5236\u5668\uFF08ICH\uFF09\u6216\u5E73\u53F0\u8DEF\u5F91\u63A7\u5236\u5668\uFF08PCH\uFF09\uFF0CNVIDIA\u7684\u7A31\u70BAMCP\uFF0CATI\u7684\u7A31\u70BAIXP/SB\uFF0CAMD\u7528FCH\uFF08Fusion Control Hub\uFF09\u4EE3\u8868AMD APU/AMD Ryzen/AMD EPYC\u7684\u5357\u6A4B\u6676\u7247\u3002 \u5357\u6A4B\u5305\u542B\u5927\u591A\u6578\u5468\u908A\u8A2D\u5099\u4ECB\u9762\u3001\u591A\u5A92\u9AD4\u63A7\u5236\u5668\u548C\u901A\u8A0A\u4ECB\u9762\u529F\u80FD\u3002\u4F8B\u5982PCI/\u4F4E\u901FPCIe\uFF08\u5982PCIe x1\uFF09\u63A7\u5236\u5668\u3001ATA/SATA\u63A7\u5236\u5668\u3001USB\u63A7\u5236\u5668\u3001\u7DB2\u8DEF\u63A7\u5236\u5668\u3001\u97F3\u6548\u63A7\u5236\u5668\u3002 \u4E2D\u9AD8\u968E\u7684\u5357\u6A4B\u53EF\u4EE5\u63D0\u4F9B\u300CFake RAID\u300D\u529F\u80FD\u3002\u82F1\u7279\u723E\u7684ICHxR\u7CFB\u5217\u5357\u6A4B\u652F\u63F4\u82F1\u7279\u5C14\u5FEB\u901F\u5B58\u50A8\u6280\u672F\u3002"@zh . "\u041F\u0456\u0432\u0434\u0435\u043D\u043D\u0438\u0439 \u043C\u0456\u0441\u0442 (\u0432\u0456\u0434 \u0430\u043D\u0433\u043B. Southbridge) (\u0444\u0443\u043D\u043A\u0446\u0456\u043E\u043D\u0430\u043B\u044C\u043D\u0438\u0439 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440) \u2014 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440-\u043A\u043E\u043D\u0446\u0435\u043D\u0442\u0440\u0430\u0442\u043E\u0440 \u0432\u0432\u0435\u0434\u0435\u043D\u043D\u044F-\u0432\u0438\u0432\u0435\u0434\u0435\u043D\u043D\u044F (\u0432\u0456\u0434 \u0430\u043D\u0433\u043B. I/O Controller Hub, ICH). \u0417\u0430\u0437\u0432\u0438\u0447\u0430\u0439 \u0446\u0435 \u043E\u0434\u043D\u0430 \u043C\u0456\u043A\u0440\u043E\u0441\u0445\u0435\u043C\u0430, \u044F\u043A\u0430 \u043F\u043E\u0432'\u044F\u0437\u0443\u0454 \u00AB\u041F\u043E\u0432\u0456\u043B\u044C\u043D\u0456\u00BB (\u043F\u043E\u0440\u0456\u0432\u043D\u044F\u043D\u043E \u0437\u0456 \u0437\u0432'\u044F\u0437\u043A\u043E\u044E \u00AB\u0426\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u0438\u0439 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440-\u041E\u0417\u041F\u00BB) \u0432\u0437\u0430\u0454\u043C\u043E\u0434\u0456\u0457 (\u043D\u0430\u043F\u0440\u0438\u043A\u043B\u0430\u0434, Low Pin Count, Super I/O \u0430\u0431\u043E \u0440\u043E\u0437'\u0454\u043C\u0438 \u0448\u0438\u043D \u0434\u043B\u044F \u043F\u0456\u0434\u043A\u043B\u044E\u0447\u0435\u043D\u043D\u044F \u043F\u0435\u0440\u0438\u0444\u0435\u0440\u0456\u0439\u043D\u0438\u0445 \u043F\u0440\u0438\u0441\u0442\u0440\u043E\u0457\u0432) \u043D\u0430 \u043C\u0430\u0442\u0435\u0440\u0438\u043D\u0441\u044C\u043A\u0456\u0439 \u043F\u043B\u0430\u0442\u0456 \u0437 \u0426\u041F\u0423 \u0447\u0435\u0440\u0435\u0437 \u041F\u0456\u0432\u043D\u0456\u0447\u043D\u0438\u0439 \u043C\u0456\u0441\u0442, \u044F\u043A\u0438\u0439, \u043D\u0430 \u0432\u0456\u0434\u043C\u0456\u043D\u0443 \u0432\u0456\u0434 \u041F\u0456\u0432\u0434\u0435\u043D\u043D\u043E\u0433\u043E, \u0437\u0430\u0437\u0432\u0438\u0447\u0430\u0439 \u043F\u0456\u0434\u043A\u043B\u044E\u0447\u0435\u043D\u0438\u0439 \u0431\u0435\u0437\u043F\u043E\u0441\u0435\u0440\u0435\u0434\u043D\u044C\u043E \u0434\u043E \u0446\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u043E\u0433\u043E \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430."@uk . . . . . . . "( \uB2E4\uB978 \uB73B\uC5D0 \uB300\uD574\uC11C\uB294 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0 (\uB9E4\uC0AC\uCD94\uC138\uCE20\uC8FC) \uBB38\uC11C\uB97C \uCC38\uACE0\uD558\uC2ED\uC2DC\uC624.) \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0(Southbridge)\uB294 \uAC1C\uC778\uC6A9 \uCEF4\uD4E8\uD130(PC)\uC758 \uCF54\uC5B4 \uB17C\uB9AC \uCE69\uC14B \uB0B4\uC758 \uB450 \uCE69\uB4E4 \uAC00\uC6B4\uB370 \uD558\uB098\uC774\uBA70, \uB2E4\uB978 \uD558\uB098\uB294 \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uC774\uB2E4. \uCEF4\uD4E8\uD130\uC5D0 \uBD80\uCC29\uB41C \uAC01\uAC01\uC758 \uC7A5\uCE58\uC640\uC758 \uC785\uCD9C\uB825\uC744 \uB2F4\uB2F9\uD55C\uB2E4. \uC778\uD154 \uCE69\uC14B\uC744 \uAC16\uCD98 \uC2DC\uC2A4\uD15C\uC5D0\uC11C\uB294 \uC785\uCD9C\uB825 \uCEE8\uD2B8\uB864\uB7EC \uD5C8\uBE0C(I/O Controller Hub, ICH)\uB77C\uACE0 \uBD80\uB974\uBA70, AMD\uC758 \uACBD\uC6B0 (AMD \uD4E8\uC804 \uB3C4\uC785 \uC774\uD6C4) \uD4E8\uC804 \uCEE8\uD2B8\uB864\uB7EC \uD5C8\uBE0C(Fusion Controller Hub)\uB85C \uBD80\uB978\uB2E4. \uC608\uB97C \uB4E4\uC5B4, \uB9C8\uC6B0\uC2A4\uB97C \uC6C0\uC9C1\uC774\uBA74 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0\uC5D0 \uADF8 \uC815\uBCF4\uAC00 \uC804\uB2EC\uB418\uBA70 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0\uB294 \uADF8 \uC815\uBCF4\uB97C \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB85C \uBCF4\uB0B4\uACE0 \uB2E4\uC2DC \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB294 \uBA54\uBAA8\uB9AC\uB85C \uBCF4\uB0B8\uB2E4. \uADF8 \uB4A4 CPU\uB294 \uBA54\uBAA8\uB9AC\uC758 \uC815\uBCF4\uB97C \uBC1B\uC544 \uC5F0\uC0B0\uC744 \uD558\uBA70, \uC774 \uC5F0\uC0B0\uB41C \uC815\uBCF4\uB97C \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB97C \uD1B5\uD574 \uADF8\uB798\uD53D \uCE74\uB4DC\uB85C \uB0B4\uBCF4\uB0B4\uACE0 \uADF8\uB798\uD53D \uCE74\uB4DC\uB294 \uB2E4\uC2DC \uBAA8\uB2C8\uD130\uB85C \uBCF4\uB0B4 \uCD9C\uB825\uD558\uAC8C \uB41C\uB2E4. \uC77C\uBC18\uC801\uC73C\uB85C \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0\uC758 \uC704\uCE58\uB294 PCI \uC2AC\uB86F \uCABD\uC5D0 \uC704\uCE58\uD574 \uC788\uB2E4. \uCD08\uAE30\uC5D0\uB294 \uBC1C\uC5F4\uC774 \uADF8\uB2E4\uC9C0 \uB192\uC9C0 \uC54A\uC544 \uBC29\uC5F4\uD310\uB4F1\uC758 \uBCC4\uB3C4\uC758 \uB0C9\uAC01\uC7A5\uCE58\uAC00 \uC874\uC7AC\uD558\uC9C0 \uC54A\uC558\uC73C\uB098, \uC785/\uCD9C\uB825 \uC18D\uB3C4\uAC00 \uBC1C\uB2EC\uD568\uC5D0 \uB530\uB77C \uBC29\uC5F4\uD310\uB4F1\uC758 \uBCC4\uB3C4\uC758 \uB0C9\uAC01\uC7A5\uCE58\uAC00 \uD544\uC694\uD558\uAC8C \uB418\uC5C8\uB2E4."@ko . "What push for SoC processors? Explain the context."@en . . . "\u041F\u0456\u0432\u0434\u0435\u043D\u043D\u0438\u0439 \u043C\u0456\u0441\u0442 (\u043A\u043E\u043C\u043F'\u044E\u0442\u0435\u0440)"@uk . . "The southbridge is one of the two chips in the core logic chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In systems with Intel chipsets, the southbridge is named I/O Controller Hub (ICH), while AMD has named its southbridge Fusion Controller Hub (FCH) since the introduction of its Fusion AMD Accelerated Processing Unit (APU) while moving the functions of the Northbridge onto the CPU die, hence making it similar in function to the Platform hub controller."@en . . . "Southbridge (ji\u017En\u00ED m\u016Fstek) je tak\u00E9 zn\u00E1m jako vstupn\u011B-v\u00FDstupn\u00ED \u0159adi\u010D (I/O Controller Hub). \u010Cip realizuje pomalej\u0161\u00ED funkce z\u00E1kladn\u00ED desky v po\u010D\u00EDta\u010Dov\u00E9 architektu\u0159e se severn\u00EDm a ji\u017En\u00EDm m\u016Fstkem. Ji\u017En\u00ED m\u016Fstek odli\u0161\u00EDme od severn\u00EDho snadno tak, \u017Ee nen\u00ED p\u0159\u00EDmo spojen s procesorem. Severn\u00ED m\u016Fstek realizuje spojen\u00ED ji\u017En\u00EDho m\u016Fstku a procesoru."@cs . . . . "Suda ponto - estas kromnomo de ico muntata en \u0109eftabulon kaj konsistanta el universala en-el-kontrolilo. La ico estas dua parto de \u0109ef\u0109iparo projektita la\u016D haba arkitekturo. Suda ponto realigas kunlaboron de diskaj interfacoj , seriaj kaj paralelaj interfacoj, busoj ka.Por kunligi sudan kaj nordan ponton estas uzataj apartaj busoj, ekz: MuTIOL, , HI 2.0, HyperTransport."@eo . . . . . . "\u03A4\u03BF southbridge, (\u03B5\u03C0\u03AF\u03C3\u03B7\u03C2 \u03B3\u03BD\u03C9\u03C3\u03C4\u03CC \u03BA\u03B1\u03B9 \u03C9\u03C2 - Input/Output Controler Hub \u03C3\u03C4\u03B1 \u03C3\u03C5\u03C3\u03C4\u03AE\u03BC\u03B1\u03C4\u03B1 \u03C4\u03B7\u03C2 Intel) \u03B5\u03AF\u03BD\u03B1\u03B9 \u03C4\u03BF \u03C4\u03C3\u03B9\u03C0 \u03C4\u03BF \u03BF\u03C0\u03BF\u03AF\u03BF \u03C5\u03BB\u03BF\u03C0\u03BF\u03B9\u03B5\u03AF \u03C4\u03B9\u03C2 \u03C0\u03B9\u03BF \u00AB\u03B1\u03C1\u03B3\u03AD\u03C2\u00BB \u03BB\u03B5\u03B9\u03C4\u03BF\u03C5\u03C1\u03B3\u03AF\u03B5\u03C2 \u03C4\u03B7\u03C2 \u03BC\u03B7\u03C4\u03C1\u03B9\u03BA\u03AE\u03C2 \u03C0\u03BB\u03B1\u03BA\u03AD\u03C4\u03B1\u03C2 (\u03C3\u03B5 \u03B1\u03C1\u03C7\u03B9\u03C4\u03B5\u03BA\u03C4\u03BF\u03BD\u03B9\u03BA\u03AE \u03C5\u03C0\u03BF\u03BB\u03BF\u03B3\u03B9\u03C3\u03C4\u03CE\u03BD \u03B2\u03B1\u03C3\u03B9\u03C3\u03BC\u03AD\u03BD\u03C9\u03BD \u03C3\u03B5 \u03C4\u03C3\u03AF\u03C0\u03C3\u03B5\u03C4 northbridge/southbridge). \u03A4\u03BF southbridge \u03C3\u03C5\u03BD\u03AE\u03B8\u03C9\u03C2 \u03B4\u03B5\u03BD \u03C3\u03C5\u03BD\u03B4\u03AD\u03B5\u03C4\u03B1\u03B9 \u03B1\u03C0\u03B5\u03C5\u03B8\u03B5\u03AF\u03B1\u03C2 \u03BC\u03B5 \u03C4\u03B7\u03BD \u039A\u039C\u0395. \u0391\u03BD\u03C4\u03B9\u03B8\u03AD\u03C4\u03C9\u03C2, \u03B5\u03C0\u03B9\u03BA\u03BF\u03B9\u03BD\u03C9\u03BD\u03B5\u03AF \u03BC\u03B5 \u03B1\u03C5\u03C4\u03AE\u03BD \u03BC\u03AD\u03C3\u03C9 \u03C4\u03BF\u03C5 northbridge. \u0395\u03C0\u03AF\u03C3\u03B7\u03C2 \u03BC\u03C0\u03BF\u03C1\u03B5\u03AF \u03BD\u03B1 \u03C3\u03C5\u03BD\u03B4\u03AD\u03B5\u03B9 \u03C4\u03B1 \u03C3\u03AE\u03BC\u03B1\u03C4\u03B1 \u03B1\u03C0\u03CC \u03C4\u03B9\u03C2 \u03C3\u03C5\u03C3\u03BA\u03B5\u03C5\u03AD\u03C2 \u03B5\u03B9\u03C3\u03CC\u03B4\u03BF\u03C5/\u03B5\u03BE\u03CC\u03B4\u03BF\u03C5 \u03B1\u03C0\u03B5\u03C5\u03B8\u03B5\u03AF\u03B1\u03C2 \u03BC\u03B5 \u03C4\u03BF\u03BD \u03B5\u03C0\u03B5\u03BE\u03B5\u03C1\u03B3\u03B1\u03C3\u03C4\u03AE, \u03BC\u03AD\u03C3\u03C9 \u03B5\u03BD\u03CC\u03C2 \u03BF\u03BB\u03BF\u03BA\u03BB\u03B7\u03C1\u03C9\u03BC\u03AD\u03BD\u03BF\u03C5 \u03BA\u03C5\u03BA\u03BB\u03CE\u03BC\u03B1\u03C4\u03BF\u03C2 \u03B5\u03BB\u03AD\u03B3\u03C7\u03BF\u03C5 \u03C4\u03C9\u03BD \u03B4\u03B9\u03B1\u03CD\u03BB\u03C9\u03BD, \u03B3\u03B9\u03B1 \u03C4\u03B7\u03BD \u03C0\u03C1\u03CC\u03C3\u03B2\u03B1\u03C3\u03B7 \u03BA\u03B1\u03B9 \u03C4\u03BF\u03BD \u03AD\u03BB\u03B5\u03B3\u03C7\u03BF \u03C4\u03C9\u03BD \u03B4\u03B5\u03B4\u03BF\u03BC\u03AD\u03BD\u03C9\u03BD."@el . . . "Mostek po\u0142udniowy"@pl . . . . . . . . . . . . . . . "Southbridge"@cs . . . "Southbridge"@it . . . "\u5357\u6865"@zh . "Inom datorteknik \u00E4r en sydbrygga ett chip som sk\u00F6ter kommunikation med periferikomponenter p\u00E5 ett moderkort f\u00F6r persondatorer (av modernare snitt). Det g\u00E4ller framf\u00F6rallt PCI-buss och h\u00E5rddisk, men \u00E4ven till exempel USB, printerportar och ev. RS-232-portar."@sv . "SouthBridge"@ca . . "Inom datorteknik \u00E4r en sydbrygga ett chip som sk\u00F6ter kommunikation med periferikomponenter p\u00E5 ett moderkort f\u00F6r persondatorer (av modernare snitt). Det g\u00E4ller framf\u00F6rallt PCI-buss och h\u00E5rddisk, men \u00E4ven till exempel USB, printerportar och ev. RS-232-portar."@sv . "\u062C\u0633\u0631 \u062C\u0646\u0648\u0628\u064A (\u0628\u0627\u0644\u0625\u0646\u062C\u0644\u064A\u0632\u064A\u0629: Southbridge)\u200F \u0648\u064A\u0639\u0631\u0641 \u0623\u064A\u0636\u0627 \u0628\u0627\u0633\u0645 I/O Controller Hub ICH \u0648 Platform Controller Hub PCH \u0641\u064A \u0634\u0631\u0643\u0629 \u0625\u0646\u062A\u0644 (\u0644\u0643\u0646 \u062A\u0633\u062A\u062E\u062F\u0645 \u0634\u0631\u0643\u0627\u062A \u0625\u064A\u0647 \u0623\u0645 \u062F\u064A \u0648 \u0648 \u0627\u0633\u0645 Southbridge). \u0648\u0647\u064A \u0631\u0642\u0627\u0642\u0629 \u0645\u0646 \u0645\u062C\u0645\u0648\u0639\u0629 \u0634\u0631\u0627\u0626\u062D \u062A\u062A\u062D\u0643\u0645 \u0628\u0645\u0643\u0648\u0646\u0627\u062A \u0644\u0648\u062D\u0629 \u0623\u0645 \u0627\u0644\u0623\u0628\u0637\u0623 \u0645\u0646 \u063A\u064A\u0631\u0647\u0627 (\u0645\u062B\u0644 \u0646\u0627\u0642\u0644 \u0645\u062A\u0633\u0644\u0633\u0644 \u0639\u0627\u0645). \u0648\u064A\u0645\u0643\u0646 \u062A\u0645\u064A\u064A\u0632\u0647 \u0641\u064A \u0644\u0648\u062D\u0629 \u0627\u0644\u0623\u0645 \u0639\u0646 \u0628\u0639\u062F\u0645 \u062A\u0648\u0627\u0635\u0644\u0647 \u0645\u0628\u0627\u0634\u0631\u0629 \u0645\u0639 \u0648\u062D\u062F\u0629 \u0627\u0644\u0645\u0639\u0627\u0644\u062C\u0629 \u0627\u0644\u0645\u0631\u0643\u0632\u064A\u0629 \u0641\u0647\u0648 \u064A\u062A\u0648\u0627\u0635\u0644 \u0645\u0639 \u0627\u0644\u062C\u0633\u0631 \u0627\u0644\u0634\u0645\u0627\u0644\u064A \u0648\u0627\u0644\u062C\u0633\u0631 \u0627\u0644\u0634\u0645\u0627\u0644\u064A \u064A\u062A\u0648\u0627\u0635\u0644 \u0645\u0639 \u0648\u062D\u062F\u0629 \u0627\u0644\u0645\u0639\u0627\u0644\u062C\u0629 \u0627\u0644\u0645\u0631\u0643\u0632\u064A\u0629."@ar . "Die Southbridge ist eine Hardwarekomponente einer PC-Hauptplatine (auch Motherboard oder Mainboard genannt). Es handelt sich um einen Integrierten Schaltkreis zur Datenverteilung. Die Southbridge befindet sich nahe an den PCI-Steckpl\u00E4tzen, um auf m\u00F6glichst kurzem Weg eine elektrische Verbindung herzustellen. Sie ist neben der Northbridge ein wichtiger Bestandteil des Mainboards. Die beiden Schaltkreise werden auch als Chipsatz bezeichnet."@de . "Le southbridge est l\u2019une des deux puces du chipset d\u2019une carte m\u00E8re dont l\u2019autre puce est le northbridge."@fr . . . . . . . "O southbridge (em portugu\u00EAs: ponte sul), tamb\u00E9m conhecido como I/O Controller Hub em sistemas Intel (AMD, VIA, SiS e outros geralmente usam southbridge), \u00E9 um chip que implementa as capacidades mais \"lentas\" da placa-m\u00E3e numa arquitetura de chipset northbridge/southbridge. O southbridge pode ser geralmente diferenciado do northbridge por n\u00E3o estar diretamente conectado \u00E0 UCP. Em vez disso, o northbridge liga o southbridge \u00E0 UCP."@pt . . . . "Die Southbridge ist eine Hardwarekomponente einer PC-Hauptplatine (auch Motherboard oder Mainboard genannt). Es handelt sich um einen Integrierten Schaltkreis zur Datenverteilung. Die Southbridge befindet sich nahe an den PCI-Steckpl\u00E4tzen, um auf m\u00F6glichst kurzem Weg eine elektrische Verbindung herzustellen. Sie ist neben der Northbridge ein wichtiger Bestandteil des Mainboards. Die beiden Schaltkreise werden auch als Chipsatz bezeichnet."@de . . "Southbridge"@nl . . . . . "\u042E\u0436\u043D\u044B\u0439 \u043C\u043E\u0441\u0442 (\u043A\u043E\u043C\u043F\u044C\u044E\u0442\u0435\u0440)"@ru . . "( \uB2E4\uB978 \uB73B\uC5D0 \uB300\uD574\uC11C\uB294 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0 (\uB9E4\uC0AC\uCD94\uC138\uCE20\uC8FC) \uBB38\uC11C\uB97C \uCC38\uACE0\uD558\uC2ED\uC2DC\uC624.) \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0(Southbridge)\uB294 \uAC1C\uC778\uC6A9 \uCEF4\uD4E8\uD130(PC)\uC758 \uCF54\uC5B4 \uB17C\uB9AC \uCE69\uC14B \uB0B4\uC758 \uB450 \uCE69\uB4E4 \uAC00\uC6B4\uB370 \uD558\uB098\uC774\uBA70, \uB2E4\uB978 \uD558\uB098\uB294 \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uC774\uB2E4. \uCEF4\uD4E8\uD130\uC5D0 \uBD80\uCC29\uB41C \uAC01\uAC01\uC758 \uC7A5\uCE58\uC640\uC758 \uC785\uCD9C\uB825\uC744 \uB2F4\uB2F9\uD55C\uB2E4. \uC778\uD154 \uCE69\uC14B\uC744 \uAC16\uCD98 \uC2DC\uC2A4\uD15C\uC5D0\uC11C\uB294 \uC785\uCD9C\uB825 \uCEE8\uD2B8\uB864\uB7EC \uD5C8\uBE0C(I/O Controller Hub, ICH)\uB77C\uACE0 \uBD80\uB974\uBA70, AMD\uC758 \uACBD\uC6B0 (AMD \uD4E8\uC804 \uB3C4\uC785 \uC774\uD6C4) \uD4E8\uC804 \uCEE8\uD2B8\uB864\uB7EC \uD5C8\uBE0C(Fusion Controller Hub)\uB85C \uBD80\uB978\uB2E4. \uC608\uB97C \uB4E4\uC5B4, \uB9C8\uC6B0\uC2A4\uB97C \uC6C0\uC9C1\uC774\uBA74 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0\uC5D0 \uADF8 \uC815\uBCF4\uAC00 \uC804\uB2EC\uB418\uBA70 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0\uB294 \uADF8 \uC815\uBCF4\uB97C \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB85C \uBCF4\uB0B4\uACE0 \uB2E4\uC2DC \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB294 \uBA54\uBAA8\uB9AC\uB85C \uBCF4\uB0B8\uB2E4. \uADF8 \uB4A4 CPU\uB294 \uBA54\uBAA8\uB9AC\uC758 \uC815\uBCF4\uB97C \uBC1B\uC544 \uC5F0\uC0B0\uC744 \uD558\uBA70, \uC774 \uC5F0\uC0B0\uB41C \uC815\uBCF4\uB97C \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB97C \uD1B5\uD574 \uADF8\uB798\uD53D \uCE74\uB4DC\uB85C \uB0B4\uBCF4\uB0B4\uACE0 \uADF8\uB798\uD53D \uCE74\uB4DC\uB294 \uB2E4\uC2DC \uBAA8\uB2C8\uD130\uB85C \uBCF4\uB0B4 \uCD9C\uB825\uD558\uAC8C \uB41C\uB2E4. \uC77C\uBC18\uC801\uC73C\uB85C \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0\uC758 \uC704\uCE58\uB294 PCI \uC2AC\uB86F \uCABD\uC5D0 \uC704\uCE58\uD574 \uC788\uB2E4. \uCD08\uAE30\uC5D0\uB294 \uBC1C\uC5F4\uC774 \uADF8\uB2E4\uC9C0 \uB192\uC9C0 \uC54A\uC544 \uBC29\uC5F4\uD310\uB4F1\uC758 \uBCC4\uB3C4\uC758 \uB0C9\uAC01\uC7A5\uCE58\uAC00 \uC874\uC7AC\uD558\uC9C0 \uC54A\uC558\uC73C\uB098, \uC785/\uCD9C\uB825 \uC18D\uB3C4\uAC00 \uBC1C\uB2EC\uD568\uC5D0 \uB530\uB77C \uBC29\uC5F4\uD310\uB4F1\uC758 \uBCC4\uB3C4\uC758 \uB0C9\uAC01\uC7A5\uCE58\uAC00 \uD544\uC694\uD558\uAC8C \uB418\uC5C8\uB2E4."@ko . "Suda ponto"@eo . . . . . . . "Southbridge"@pt . . "Southbridge"@de . . "Southbridge (chiamato anche ICH da I/O Controller Hub), \u00E8 un chip, che \u00E8 parte del chipset, che implementa le capacit\u00E0 pi\u00F9 \"lente\" di una scheda madre, come il collegamento con i bus PCI e USB, i canali ATA, le porte seriali e parallele, il floppy disk e tutti i dispositivi esterni, in un'architettura basata su un chipset northbrige/southbridge. Generalmente il southbridge \u00E8 legato alla CPU tramite il northbridge, il quale invece dialoga direttamente con il processore e la memoria RAM."@it . . . "Suda ponto - estas kromnomo de ico muntata en \u0109eftabulon kaj konsistanta el universala en-el-kontrolilo. La ico estas dua parto de \u0109ef\u0109iparo projektita la\u016D haba arkitekturo. Suda ponto realigas kunlaboron de diskaj interfacoj , seriaj kaj paralelaj interfacoj, busoj ka.Por kunligi sudan kaj nordan ponton estas uzataj apartaj busoj, ekz: MuTIOL, , HI 2.0, HyperTransport."@eo . "Southbridge (computing)"@en . "\u062C\u0633\u0631 \u062C\u0646\u0648\u0628\u064A (\u062D\u0627\u0633\u0648\u0628)"@ar . "\u062C\u0633\u0631 \u062C\u0646\u0648\u0628\u064A (\u0628\u0627\u0644\u0625\u0646\u062C\u0644\u064A\u0632\u064A\u0629: Southbridge)\u200F \u0648\u064A\u0639\u0631\u0641 \u0623\u064A\u0636\u0627 \u0628\u0627\u0633\u0645 I/O Controller Hub ICH \u0648 Platform Controller Hub PCH \u0641\u064A \u0634\u0631\u0643\u0629 \u0625\u0646\u062A\u0644 (\u0644\u0643\u0646 \u062A\u0633\u062A\u062E\u062F\u0645 \u0634\u0631\u0643\u0627\u062A \u0625\u064A\u0647 \u0623\u0645 \u062F\u064A \u0648 \u0648 \u0627\u0633\u0645 Southbridge). \u0648\u0647\u064A \u0631\u0642\u0627\u0642\u0629 \u0645\u0646 \u0645\u062C\u0645\u0648\u0639\u0629 \u0634\u0631\u0627\u0626\u062D \u062A\u062A\u062D\u0643\u0645 \u0628\u0645\u0643\u0648\u0646\u0627\u062A \u0644\u0648\u062D\u0629 \u0623\u0645 \u0627\u0644\u0623\u0628\u0637\u0623 \u0645\u0646 \u063A\u064A\u0631\u0647\u0627 (\u0645\u062B\u0644 \u0646\u0627\u0642\u0644 \u0645\u062A\u0633\u0644\u0633\u0644 \u0639\u0627\u0645). \u0648\u064A\u0645\u0643\u0646 \u062A\u0645\u064A\u064A\u0632\u0647 \u0641\u064A \u0644\u0648\u062D\u0629 \u0627\u0644\u0623\u0645 \u0639\u0646 \u0628\u0639\u062F\u0645 \u062A\u0648\u0627\u0635\u0644\u0647 \u0645\u0628\u0627\u0634\u0631\u0629 \u0645\u0639 \u0648\u062D\u062F\u0629 \u0627\u0644\u0645\u0639\u0627\u0644\u062C\u0629 \u0627\u0644\u0645\u0631\u0643\u0632\u064A\u0629 \u0641\u0647\u0648 \u064A\u062A\u0648\u0627\u0635\u0644 \u0645\u0639 \u0627\u0644\u062C\u0633\u0631 \u0627\u0644\u0634\u0645\u0627\u0644\u064A \u0648\u0627\u0644\u062C\u0633\u0631 \u0627\u0644\u0634\u0645\u0627\u0644\u064A \u064A\u062A\u0648\u0627\u0635\u0644 \u0645\u0639 \u0648\u062D\u062F\u0629 \u0627\u0644\u0645\u0639\u0627\u0644\u062C\u0629 \u0627\u0644\u0645\u0631\u0643\u0632\u064A\u0629."@ar . . . "De southbridge verzorgde de communicatie met de relatief tragere componenten van de pc: de harde schijven, diskettestations, toetsenbord, USB en de andere PCI-sleuven (Engels: slots) naast de AGP en PCI-Express (ook wel PCI-e). De southbridge vormde samen met de northbridge de chipset op het moederbord. Sinds de introductie van de Sandy Bridge processoren in 2011, is de northbridge in de SoC van de CPU ge\u00EFntegreerd. Sinds de introductie van chipsets in 2008, is de southbridge door Intel vervangen door de (PCH). Tot de functionaliteit van een southbridge anno 2005 behoorde:"@nl . . . "The southbridge is one of the two chips in the core logic chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In systems with Intel chipsets, the southbridge is named I/O Controller Hub (ICH), while AMD has named its southbridge Fusion Controller Hub (FCH) since the introduction of its Fusion AMD Accelerated Processing Unit (APU) while moving the functions of the Northbridge onto the CPU die, hence making it similar in function to the Platform hub controller. The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access."@en . . . . "Mostek po\u0142udniowy (ang. southbridge) \u2013 element wsp\u00F3\u0142czesnych chipset\u00F3w, realizuj\u0105cy po\u0142\u0105czenie procesora do wolniejszej cz\u0119\u015Bci wyposa\u017Cenia mikrokomputera: \n* nap\u0119d\u00F3w dysk\u00F3w twardych (z\u0142\u0105cza IDE/ATA/SATA/ATAPI) \n* magistral ISA, PCI \n* sterownika przerwa\u0144 \n* sterownika DMA \n* nieulotnej pami\u0119ci BIOS \n* modu\u0142u zegara czasu rzeczywistego Opcjonalnie mostek po\u0142udniowy mo\u017Ce obs\u0142ugiwa\u0107 r\u00F3wnie\u017C: \n* magistral\u0119 FireWire \n* magistral\u0119 USB \n* z\u0142\u0105cze do sterownika RAID \n* z\u0142\u0105cze Ethernet W rzadkich przypadkach mostek po\u0142udniowy obs\u0142uguje tak\u017Ce zewn\u0119trzne z\u0142\u0105cza szeregowe, w tym z\u0142\u0105cza myszy i klawiatury oraz RS-232 \u2013 zazwyczaj jednak urz\u0105dzenia te do\u0142\u0105czane s\u0105 do mostka po\u0142udniowego przez dodatkowy uk\u0142ad nazywany SIO (ang. Super Input/Output). Przez SIO obs\u0142ugiwane s\u0105 r\u00F3wnie\u017C z\u0142\u0105cza r\u00F3wnoleg\u0142e (port Centronics), \u0142\u0105cze podczerwieni (IrDA), stacje dyskietek i Flash ROM BIOS-u. W systemach z chipsetami Intela mostek po\u0142udniowy nosi nazw\u0119 I/O Controller Hub (ICH), natomiast AMD nazwa\u0142 go Fusion Controller Hub (FCH), co nast\u0105pi\u0142o po wprowadzeniu AMD Accelerated Processing Unit (APU)."@pl . . . . "\u041F\u0456\u0432\u0434\u0435\u043D\u043D\u0438\u0439 \u043C\u0456\u0441\u0442 (\u0432\u0456\u0434 \u0430\u043D\u0433\u043B. Southbridge) (\u0444\u0443\u043D\u043A\u0446\u0456\u043E\u043D\u0430\u043B\u044C\u043D\u0438\u0439 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440) \u2014 \u043A\u043E\u043D\u0442\u0440\u043E\u043B\u0435\u0440-\u043A\u043E\u043D\u0446\u0435\u043D\u0442\u0440\u0430\u0442\u043E\u0440 \u0432\u0432\u0435\u0434\u0435\u043D\u043D\u044F-\u0432\u0438\u0432\u0435\u0434\u0435\u043D\u043D\u044F (\u0432\u0456\u0434 \u0430\u043D\u0433\u043B. I/O Controller Hub, ICH). \u0417\u0430\u0437\u0432\u0438\u0447\u0430\u0439 \u0446\u0435 \u043E\u0434\u043D\u0430 \u043C\u0456\u043A\u0440\u043E\u0441\u0445\u0435\u043C\u0430, \u044F\u043A\u0430 \u043F\u043E\u0432'\u044F\u0437\u0443\u0454 \u00AB\u041F\u043E\u0432\u0456\u043B\u044C\u043D\u0456\u00BB (\u043F\u043E\u0440\u0456\u0432\u043D\u044F\u043D\u043E \u0437\u0456 \u0437\u0432'\u044F\u0437\u043A\u043E\u044E \u00AB\u0426\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u0438\u0439 \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440-\u041E\u0417\u041F\u00BB) \u0432\u0437\u0430\u0454\u043C\u043E\u0434\u0456\u0457 (\u043D\u0430\u043F\u0440\u0438\u043A\u043B\u0430\u0434, Low Pin Count, Super I/O \u0430\u0431\u043E \u0440\u043E\u0437'\u0454\u043C\u0438 \u0448\u0438\u043D \u0434\u043B\u044F \u043F\u0456\u0434\u043A\u043B\u044E\u0447\u0435\u043D\u043D\u044F \u043F\u0435\u0440\u0438\u0444\u0435\u0440\u0456\u0439\u043D\u0438\u0445 \u043F\u0440\u0438\u0441\u0442\u0440\u043E\u0457\u0432) \u043D\u0430 \u043C\u0430\u0442\u0435\u0440\u0438\u043D\u0441\u044C\u043A\u0456\u0439 \u043F\u043B\u0430\u0442\u0456 \u0437 \u0426\u041F\u0423 \u0447\u0435\u0440\u0435\u0437 \u041F\u0456\u0432\u043D\u0456\u0447\u043D\u0438\u0439 \u043C\u0456\u0441\u0442, \u044F\u043A\u0438\u0439, \u043D\u0430 \u0432\u0456\u0434\u043C\u0456\u043D\u0443 \u0432\u0456\u0434 \u041F\u0456\u0432\u0434\u0435\u043D\u043D\u043E\u0433\u043E, \u0437\u0430\u0437\u0432\u0438\u0447\u0430\u0439 \u043F\u0456\u0434\u043A\u043B\u044E\u0447\u0435\u043D\u0438\u0439 \u0431\u0435\u0437\u043F\u043E\u0441\u0435\u0440\u0435\u0434\u043D\u044C\u043E \u0434\u043E \u0446\u0435\u043D\u0442\u0440\u0430\u043B\u044C\u043D\u043E\u0433\u043E \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430."@uk . "SouthBridge \u00E9s la part del joc de xips que controla el sistema d'entrada/eixida de dades, el bus d'IDE i en conseq\u00FC\u00E8ncia, als dispositius d'emmagatzemament, l'\u00E0udio i altres busos, com el Bus s\u00E8rie universal, el ISA, el port s\u00E8rie, el port paral\u00B7lel, etc. El seu nom es deu al fet que la seua localitzaci\u00F3 habitual \u00E9s a la zona sur del conjunt Chipset en la placa mare."@ca . . . "514041"^^ . "\u03A4\u03BF southbridge, (\u03B5\u03C0\u03AF\u03C3\u03B7\u03C2 \u03B3\u03BD\u03C9\u03C3\u03C4\u03CC \u03BA\u03B1\u03B9 \u03C9\u03C2 - Input/Output Controler Hub \u03C3\u03C4\u03B1 \u03C3\u03C5\u03C3\u03C4\u03AE\u03BC\u03B1\u03C4\u03B1 \u03C4\u03B7\u03C2 Intel) \u03B5\u03AF\u03BD\u03B1\u03B9 \u03C4\u03BF \u03C4\u03C3\u03B9\u03C0 \u03C4\u03BF \u03BF\u03C0\u03BF\u03AF\u03BF \u03C5\u03BB\u03BF\u03C0\u03BF\u03B9\u03B5\u03AF \u03C4\u03B9\u03C2 \u03C0\u03B9\u03BF \u00AB\u03B1\u03C1\u03B3\u03AD\u03C2\u00BB \u03BB\u03B5\u03B9\u03C4\u03BF\u03C5\u03C1\u03B3\u03AF\u03B5\u03C2 \u03C4\u03B7\u03C2 \u03BC\u03B7\u03C4\u03C1\u03B9\u03BA\u03AE\u03C2 \u03C0\u03BB\u03B1\u03BA\u03AD\u03C4\u03B1\u03C2 (\u03C3\u03B5 \u03B1\u03C1\u03C7\u03B9\u03C4\u03B5\u03BA\u03C4\u03BF\u03BD\u03B9\u03BA\u03AE \u03C5\u03C0\u03BF\u03BB\u03BF\u03B3\u03B9\u03C3\u03C4\u03CE\u03BD \u03B2\u03B1\u03C3\u03B9\u03C3\u03BC\u03AD\u03BD\u03C9\u03BD \u03C3\u03B5 \u03C4\u03C3\u03AF\u03C0\u03C3\u03B5\u03C4 northbridge/southbridge). \u03A4\u03BF southbridge \u03C3\u03C5\u03BD\u03AE\u03B8\u03C9\u03C2 \u03B4\u03B5\u03BD \u03C3\u03C5\u03BD\u03B4\u03AD\u03B5\u03C4\u03B1\u03B9 \u03B1\u03C0\u03B5\u03C5\u03B8\u03B5\u03AF\u03B1\u03C2 \u03BC\u03B5 \u03C4\u03B7\u03BD \u039A\u039C\u0395. \u0391\u03BD\u03C4\u03B9\u03B8\u03AD\u03C4\u03C9\u03C2, \u03B5\u03C0\u03B9\u03BA\u03BF\u03B9\u03BD\u03C9\u03BD\u03B5\u03AF \u03BC\u03B5 \u03B1\u03C5\u03C4\u03AE\u03BD \u03BC\u03AD\u03C3\u03C9 \u03C4\u03BF\u03C5 northbridge. \u0395\u03C0\u03AF\u03C3\u03B7\u03C2 \u03BC\u03C0\u03BF\u03C1\u03B5\u03AF \u03BD\u03B1 \u03C3\u03C5\u03BD\u03B4\u03AD\u03B5\u03B9 \u03C4\u03B1 \u03C3\u03AE\u03BC\u03B1\u03C4\u03B1 \u03B1\u03C0\u03CC \u03C4\u03B9\u03C2 \u03C3\u03C5\u03C3\u03BA\u03B5\u03C5\u03AD\u03C2 \u03B5\u03B9\u03C3\u03CC\u03B4\u03BF\u03C5/\u03B5\u03BE\u03CC\u03B4\u03BF\u03C5 \u03B1\u03C0\u03B5\u03C5\u03B8\u03B5\u03AF\u03B1\u03C2 \u03BC\u03B5 \u03C4\u03BF\u03BD \u03B5\u03C0\u03B5\u03BE\u03B5\u03C1\u03B3\u03B1\u03C3\u03C4\u03AE, \u03BC\u03AD\u03C3\u03C9 \u03B5\u03BD\u03CC\u03C2 \u03BF\u03BB\u03BF\u03BA\u03BB\u03B7\u03C1\u03C9\u03BC\u03AD\u03BD\u03BF\u03C5 \u03BA\u03C5\u03BA\u03BB\u03CE\u03BC\u03B1\u03C4\u03BF\u03C2 \u03B5\u03BB\u03AD\u03B3\u03C7\u03BF\u03C5 \u03C4\u03C9\u03BD \u03B4\u03B9\u03B1\u03CD\u03BB\u03C9\u03BD, \u03B3\u03B9\u03B1 \u03C4\u03B7\u03BD \u03C0\u03C1\u03CC\u03C3\u03B2\u03B1\u03C3\u03B7 \u03BA\u03B1\u03B9 \u03C4\u03BF\u03BD \u03AD\u03BB\u03B5\u03B3\u03C7\u03BF \u03C4\u03C9\u03BD \u03B4\u03B5\u03B4\u03BF\u03BC\u03AD\u03BD\u03C9\u03BD."@el . . "Southbridge (informatique)"@fr . "Puente sur"@es . . . "O southbridge (em portugu\u00EAs: ponte sul), tamb\u00E9m conhecido como I/O Controller Hub em sistemas Intel (AMD, VIA, SiS e outros geralmente usam southbridge), \u00E9 um chip que implementa as capacidades mais \"lentas\" da placa-m\u00E3e numa arquitetura de chipset northbridge/southbridge. O southbridge pode ser geralmente diferenciado do northbridge por n\u00E3o estar diretamente conectado \u00E0 UCP. Em vez disso, o northbridge liga o southbridge \u00E0 UCP."@pt . . . "De southbridge verzorgde de communicatie met de relatief tragere componenten van de pc: de harde schijven, diskettestations, toetsenbord, USB en de andere PCI-sleuven (Engels: slots) naast de AGP en PCI-Express (ook wel PCI-e). De southbridge vormde samen met de northbridge de chipset op het moederbord. Sinds de introductie van de Sandy Bridge processoren in 2011, is de northbridge in de SoC van de CPU ge\u00EFntegreerd. Sinds de introductie van chipsets in 2008, is de southbridge door Intel vervangen door de (PCH). Tot de functionaliteit van een southbridge anno 2005 behoorde: \n* PCI-bus \n* ISA-bus \n* \n* DMA-controller \n* Interruptcontroller \n* IDE-controller (SATA of PATA) \n* \n* Realtimeklok \n* powermanagement (APM en ) \n* De southbridge kan ook directe ondersteuning voor Ethernet, RAID, USB, audiocodec, en firewire bevatten. Een enkele keer bevat de southbridge directe ondersteuning van toetsenbord, muis en seri\u00EBle poorten, maar doorgaans worden deze aangesloten door middel van de ."@nl . . . . . "El Southbridge o puente sur, tambi\u00E9n conocido como Concentrador de Controladores de Entrada/Salida (I/O Controller Hub, ICH), es un circuito integrado que se encarga de coordinar los diferentes dispositivos de entrada y salida y algunas otras funcionalidades de baja velocidad dentro de la tarjeta madre. El southbridge no est\u00E1 conectado a la CPU y se comunica con ella indirectamente a trav\u00E9s del northbridge - Puente Norte. La funcionalidad encontrada en los southbridges actuales incluye soporte para: ejemplos: \n* Bus PCI \n* Bus ISA \n* Bus SPI \n* System Management Bus ( SMBus ) \n* Controlador DMA \n* Controlador de Interrupciones \n* Controlador IDE (SATA o PATA) \n* Puente LPC \n* Reloj en Tiempo Real - Real Time Clock \n* Administraci\u00F3n de potencia el\u00E9ctrica APM y ACPI \n* BIOS \n* Interfaz de sonido o . Adicionalmente el southbridge puede incluir soporte para Ethernet, RAID, USB y Codec de Audio. El southbridge algunas veces incluye soporte para el teclado, el rat\u00F3n y los puertos seriales, sin embargo, a\u00FAn en el 2007 los computadores personales (PC) gestionaban esos recursos por medio de otro dispositivo conocido como Super I/O. En los \u00FAltimos modelos de placas el Southbridge integra cada vez mayor n\u00FAmero de dispositivos a conectar y comunicar por lo que fabricantes como AMD o VIA Technologies han desarrollado tecnolog\u00EDas como HyperTransport o respectivamente para evitar el efecto cuello de botella que se produc\u00EDa al usar como puente el bus PCI."@es . "Southbridge (chiamato anche ICH da I/O Controller Hub), \u00E8 un chip, che \u00E8 parte del chipset, che implementa le capacit\u00E0 pi\u00F9 \"lente\" di una scheda madre, come il collegamento con i bus PCI e USB, i canali ATA, le porte seriali e parallele, il floppy disk e tutti i dispositivi esterni, in un'architettura basata su un chipset northbrige/southbridge. Generalmente il southbridge \u00E8 legato alla CPU tramite il northbridge, il quale invece dialoga direttamente con il processore e la memoria RAM."@it . . . . . .