. . "16"^^ . "OpenRISC"@fr . . . . "16226"^^ . . "1.3"^^ . . . "OpenRISC \u00E9s un disseny de CPU RISC d'especificaci\u00F3 , realitzat per OpenCores i publicat sota la llic\u00E8ncia LGPL. El disseny est\u00E8 implementat amb el llenguatge de descripci\u00F3 de hardware (HDL) verilog, ha estat fabricat exitosament tant com circuit integrat ASIC com implementat mitjan\u00E7ant entorns FPGA. La ha estat portada a OpenRISC per permetre el desenvolupament en diferents llenguatges. Linux i uClinux han estat tamb\u00E9 portats a aquest processador."@ca . . . . . . . . . . . . . . "OpenRISC"@en . . . "411760"^^ . "Optional"@en . "Originally Damjan Lampret, now the OpenRISC Community"@en . . . "OpenRISC est le projet phare originel de la communaut\u00E9 (en). Il a pour but de d\u00E9velopper une s\u00E9rie d'architectures CPU RISC open source \u00E0 usage g\u00E9n\u00E9ral. La premi\u00E8re (et jusqu'\u00E0 maintenant l'unique) description d'architecture publi\u00E9e est celle de l'OpenRISC 1000, d\u00E9crivant une famille de processeurs 32 et 64 bits avec en option le support de la virgule flottante et des vecteurs. Une \u00E9quipe d'OpenCores en a fourni la premi\u00E8re impl\u00E9mentation, l' (en), \u00E9crite en langage de description de mat\u00E9riel Verilog. Le design hardware a \u00E9t\u00E9 publi\u00E9 sous la Licence publique g\u00E9n\u00E9rale limit\u00E9e GNU, alors que les mod\u00E8les et le firmware a \u00E9t\u00E9 publi\u00E9 sous Licence publique g\u00E9n\u00E9rale GNU. Une impl\u00E9mentation de r\u00E9f\u00E9rence sur SoC, bas\u00E9e sur l'OpenRISC 1200 a \u00E9t\u00E9 d\u00E9velopp\u00E9e, connue sous le nom de ORPSoC (the OpenRISC Reference Platform System-on-Chip). Un certain nombre de groupes a r\u00E9ussi \u00E0 faire une d\u00E9monstration de l'ORPSoC et d'autres conceptions bas\u00E9es sur le OR1200 sur FPGA."@fr . . "32"^^ . . . "OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community. The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL). Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC."@en . . "8"^^ . . . . . . . . . "OpenRISC ist ein Projekt der -Entwickler-Community. Das Ziel des Projekts ist die Entwicklung einer hochkonfigurierbaren RISC-CPU als Open Hardware. Die bisher einzige fertiggestellte Architektur ist die OpenRISC-1000-Familie (kurz OR1k), die als 32- und 64-Bit-Version verf\u00FCgbar ist.Das Design des OpenRISC 1200 (kurz OR1200) war das erste, das in der Hardwarebeschreibungssprache Verilog unter der GNU Lesser General Public License (GNU LGPL) ver\u00F6ffentlicht wurde. Die Firmware und der Microcode zum Prozessor wurden unter der GNU General Public License (GNU GPL) bereitgestellt. Basierend auf dem OpenRISC 1200 wurde eine System-on-a-Chip-Variante mit der Bezeichnung ORPSoC (= OpenRISC Reference Platform System-on-Chip) entwickelt. Auf beiden Varianten wurde der Betrieb eines Linux-Systems erfo"@de . . . "ORFPX32/64, ORVDX64"@en . "OpenRISC"@ru . . . . . . . . "OpenRISC es un dise\u00F1o de CPU RISC de especificaci\u00F3n libre, realizado por OpenCores y publicado bajo la licencia LGPL. El dise\u00F1o est\u00E1 implementado en el lenguaje de descripci\u00F3n de hardware verilog y ha sido fabricado exitosamente tanto como circuito integrado ASIC como implementado mediante entornos FPGA. La GNU toolchain ha sido portada a OpenRISC para permitir el desarrollo en distintos lenguajes. Linux y \u03BCCLinux han sido tambi\u00E9n portados a este procesador."@es . . . . . . "OpenRISC \u2014 \u043E\u0442\u043A\u0440\u044B\u0442\u044B\u0439 \u043C\u0438\u043A\u0440\u043E\u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440 \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u044B RISC \u0441 \u043E\u0442\u043A\u0440\u044B\u0442\u044B\u043C \u0438\u0441\u0445\u043E\u0434\u043D\u044B\u043C \u043A\u043E\u0434\u043E\u043C \u043D\u0430 \u044F\u0437\u044B\u043A\u0435 \u043E\u043F\u0438\u0441\u0430\u043D\u0438\u044F \u0430\u043F\u043F\u0430\u0440\u0430\u0442\u043D\u043E\u0433\u043E \u043E\u0431\u0435\u0441\u043F\u0435\u0447\u0435\u043D\u0438\u044F Verilog. \u041F\u0440\u043E\u0435\u043A\u0442 \u0441\u043E\u0437\u0434\u0430\u043D \u0441\u043E\u043E\u0431\u0449\u0435\u0441\u0442\u0432\u043E\u043C OpenCores \u0438 \u0440\u0430\u0441\u043F\u0440\u043E\u0441\u0442\u0440\u0430\u043D\u044F\u0435\u0442\u0441\u044F \u043F\u043E \u043B\u0438\u0446\u0435\u043D\u0437\u0438\u0438 GNU LGPL. OpenRISC \u0432\u043E\u043F\u043B\u043E\u0449\u0451\u043D \u0430\u043F\u043F\u0430\u0440\u0430\u0442\u043D\u043E \u0438 \u0443\u0441\u043F\u0435\u0448\u043D\u043E \u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u0442\u0441\u044F \u0432 \u0432\u0438\u0434\u0435 \u0438\u043D\u0442\u0435\u0433\u0440\u0430\u043B\u044C\u043D\u044B\u0445 \u043C\u0438\u043A\u0440\u043E\u0441\u0445\u0435\u043C \u0438 \u041F\u041B\u0418\u0421. \u0415\u0434\u0438\u043D\u0441\u0442\u0432\u0435\u043D\u043D\u0430\u044F \u0432\u0435\u0440\u0441\u0438\u044F \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u044B, OpenRISC 1000 (or1k), \u043E\u043F\u0438\u0441\u044B\u0432\u0430\u0435\u0442 \u0441\u0435\u043C\u0435\u0439\u0441\u0442\u0432\u043E 32- \u0438 64-\u0431\u0438\u0442\u043D\u044B\u0445 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 \u0441 \u043E\u043F\u0446\u0438\u043E\u043D\u0430\u043B\u044C\u043D\u044B\u043C\u0438 \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043D\u0438\u044F\u043C\u0438: \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u043A\u043E\u0439 \u0432\u044B\u0447\u0438\u0441\u043B\u0435\u043D\u0438\u0439 \u043D\u0430\u0434 \u0447\u0438\u0441\u043B\u0430\u043C\u0438 \u0441 \u043F\u043B\u0430\u0432\u0430\u044E\u0449\u0435\u0439 \u0437\u0430\u043F\u044F\u0442\u043E\u0439 \u0438 \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u043A\u043E\u0439 \u0432\u0435\u043A\u0442\u043E\u0440\u043D\u044B\u0445 \u043E\u043F\u0435\u0440\u0430\u0446\u0438\u0439. OpenRISC \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442\u0441\u044F \u044F\u0434\u0440\u043E\u043C linux \u043D\u0430\u0447\u0438\u043D\u0430\u044F \u0441 \u0432\u0435\u0440\u0441\u0438\u0438 3.1."@ru . . . . "1115290881"^^ . "OpenRISC es un dise\u00F1o de CPU RISC de especificaci\u00F3n libre, realizado por OpenCores y publicado bajo la licencia LGPL. El dise\u00F1o est\u00E1 implementado en el lenguaje de descripci\u00F3n de hardware verilog y ha sido fabricado exitosamente tanto como circuito integrado ASIC como implementado mediante entornos FPGA. La GNU toolchain ha sido portada a OpenRISC para permitir el desarrollo en distintos lenguajes. Linux y \u03BCCLinux han sido tambi\u00E9n portados a este procesador."@es . . "OpenRISC\u306FOpenCores\u30B3\u30DF\u30E5\u30CB\u30C6\u30A3\u306E\u5143\u3005\u306E\u65D7\u8266\u30D7\u30ED\u30B8\u30A7\u30AF\u30C8\u3067\u3042\u308B\u3002\u3053\u306E\u30D7\u30ED\u30B8\u30A7\u30AF\u30C8\u306E\u76EE\u7684\u306F\u3001\u4E00\u9023\u306E\u6C4E\u7528\u306E\u30AA\u30FC\u30D7\u30F3\u30BD\u30FC\u30B9\u306ERISC CPU\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u3092\u958B\u767A\u3059\u308B\u3053\u3068\u3067\u3042\u308B\u3002\u6700\u521D\u3067\u73FE\u5728\u306E\u3068\u3053\u308D\u552F\u4E00\u306E\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u306F\u3001OpenRISC 1000\u3067\u3042\u308B\u3002\u3053\u308C\u306F\u3001 32\u30D3\u30C3\u30C8\u306864\u30D3\u30C3\u30C8\u304C\u3042\u308A\u3001\u30AA\u30D7\u30B7\u30E7\u30F3\u3068\u3057\u3066\u6D6E\u52D5\u5C0F\u6570\u70B9\u6F14\u7B97\u3068\u30D9\u30AF\u30C8\u30EB\u6F14\u7B97\u3092\u6301\u3064\u30D5\u30A1\u30DF\u30EA\u3067\u3042\u308B\u3002 OpenCores\u306E\u30C1\u30FC\u30E0\u306F\u6700\u521D\u306E\u5B9F\u88C5\u3067\u3042\u308B\u3092\u63D0\u4F9B\u3057\u3066\u3044\u308B\u3002\u3053\u308C\u306FVerilog\u30CF\u30FC\u30C9\u30A6\u30A7\u30A2\u8A18\u8FF0\u8A00\u8A9E\u3067\u66F8\u304B\u308C\u3066\u3044\u308B\u3002\u30CF\u30FC\u30C9\u30A6\u30A7\u30A2\u306E\u30C7\u30B6\u30A4\u30F3\u306F\u3001GNU Lesser General Public License\u3067\u30EA\u30EA\u30FC\u30B9\u3055\u308C\u305F\u304C\u3001\u30E2\u30C7\u30EB\u3068\u30D5\u30A1\u30FC\u30E0\u30A6\u30A7\u30A2\u306FGNU General Public License\u3067\u30EA\u30EA\u30FC\u30B9\u3055\u308C\u305F\u3002\u30EA\u30D5\u30A1\u30EC\u30F3\u30B9\u306ESoC\u306E\u5B9F\u88C5\u306FOpenRISC 1200\u30D9\u30FC\u30B9\u3067\u958B\u767A\u3055\u308C\u3001ORPSoC (the OpenRISC Reference Platform System-on-Chip)\u3068\u3057\u3066\u77E5\u3089\u308C\u3066\u3044\u308B\u3002ORPSoC\u3084\u4ED6\u306EOpenRISC 1200\u30D9\u30FC\u30B9\u306E\u30C7\u30B6\u30A4\u30F3\u306E\u30C7\u30E2\u30F3\u30B9\u30C8\u30EC\u30FC\u30B7\u30E7\u30F3\u3092\u3057\u305F\u30B0\u30EB\u30FC\u30D7\u306F\u3001FPGA\u4E0A\u3067\u52D5\u304B\u3057\u3066\u3044\u305F\u3002."@ja . . . . . . . . . . . . "OpenRISC \u00E9s un disseny de CPU RISC d'especificaci\u00F3 , realitzat per OpenCores i publicat sota la llic\u00E8ncia LGPL. El disseny est\u00E8 implementat amb el llenguatge de descripci\u00F3 de hardware (HDL) verilog, ha estat fabricat exitosament tant com circuit integrat ASIC com implementat mitjan\u00E7ant entorns FPGA. La ha estat portada a OpenRISC per permetre el desenvolupament en diferents llenguatges. Linux i uClinux han estat tamb\u00E9 portats a aquest processador."@ca . . . . . . "OpenRISC \u2014 \u043E\u0442\u043A\u0440\u044B\u0442\u044B\u0439 \u043C\u0438\u043A\u0440\u043E\u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440 \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u044B RISC \u0441 \u043E\u0442\u043A\u0440\u044B\u0442\u044B\u043C \u0438\u0441\u0445\u043E\u0434\u043D\u044B\u043C \u043A\u043E\u0434\u043E\u043C \u043D\u0430 \u044F\u0437\u044B\u043A\u0435 \u043E\u043F\u0438\u0441\u0430\u043D\u0438\u044F \u0430\u043F\u043F\u0430\u0440\u0430\u0442\u043D\u043E\u0433\u043E \u043E\u0431\u0435\u0441\u043F\u0435\u0447\u0435\u043D\u0438\u044F Verilog. \u041F\u0440\u043E\u0435\u043A\u0442 \u0441\u043E\u0437\u0434\u0430\u043D \u0441\u043E\u043E\u0431\u0449\u0435\u0441\u0442\u0432\u043E\u043C OpenCores \u0438 \u0440\u0430\u0441\u043F\u0440\u043E\u0441\u0442\u0440\u0430\u043D\u044F\u0435\u0442\u0441\u044F \u043F\u043E \u043B\u0438\u0446\u0435\u043D\u0437\u0438\u0438 GNU LGPL. OpenRISC \u0432\u043E\u043F\u043B\u043E\u0449\u0451\u043D \u0430\u043F\u043F\u0430\u0440\u0430\u0442\u043D\u043E \u0438 \u0443\u0441\u043F\u0435\u0448\u043D\u043E \u043F\u0440\u043E\u0438\u0437\u0432\u043E\u0434\u0438\u0442\u0441\u044F \u0432 \u0432\u0438\u0434\u0435 \u0438\u043D\u0442\u0435\u0433\u0440\u0430\u043B\u044C\u043D\u044B\u0445 \u043C\u0438\u043A\u0440\u043E\u0441\u0445\u0435\u043C \u0438 \u041F\u041B\u0418\u0421. \u0415\u0434\u0438\u043D\u0441\u0442\u0432\u0435\u043D\u043D\u0430\u044F \u0432\u0435\u0440\u0441\u0438\u044F \u0430\u0440\u0445\u0438\u0442\u0435\u043A\u0442\u0443\u0440\u044B, OpenRISC 1000 (or1k), \u043E\u043F\u0438\u0441\u044B\u0432\u0430\u0435\u0442 \u0441\u0435\u043C\u0435\u0439\u0441\u0442\u0432\u043E 32- \u0438 64-\u0431\u0438\u0442\u043D\u044B\u0445 \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 \u0441 \u043E\u043F\u0446\u0438\u043E\u043D\u0430\u043B\u044C\u043D\u044B\u043C\u0438 \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043D\u0438\u044F\u043C\u0438: \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u043A\u043E\u0439 \u0432\u044B\u0447\u0438\u0441\u043B\u0435\u043D\u0438\u0439 \u043D\u0430\u0434 \u0447\u0438\u0441\u043B\u0430\u043C\u0438 \u0441 \u043F\u043B\u0430\u0432\u0430\u044E\u0449\u0435\u0439 \u0437\u0430\u043F\u044F\u0442\u043E\u0439 \u0438 \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u043A\u043E\u0439 \u0432\u0435\u043A\u0442\u043E\u0440\u043D\u044B\u0445 \u043E\u043F\u0435\u0440\u0430\u0446\u0438\u0439. \u041A\u043E\u043C\u0430\u043D\u0434\u0430 \u0440\u0430\u0437\u0440\u0430\u0431\u043E\u0442\u0447\u0438\u043A\u043E\u0432 OpenCores \u043E\u043F\u0443\u0431\u043B\u0438\u043A\u043E\u0432\u0430\u043B\u043E \u043F\u0435\u0440\u0432\u0443\u044E \u0440\u0435\u0430\u043B\u0438\u0437\u0430\u0446\u0438\u044E, , \u043D\u0430\u043F\u0438\u0441\u0430\u043D\u043D\u0443\u044E \u043D\u0430 \u044F\u0437\u044B\u043A\u0435 Verilog. \u0410\u043F\u043F\u0430\u0440\u0430\u0442\u043D\u0430\u044F \u0447\u0430\u0441\u0442\u044C \u043F\u0440\u043E\u0435\u043A\u0442\u0430 \u0438\u043C\u0435\u0435\u0442 \u043B\u0438\u0446\u0435\u043D\u0437\u0438\u044E LGPL, \u043C\u043E\u0434\u0435\u043B\u0438 \u0438 \u043F\u0440\u043E\u0448\u0438\u0432\u043A\u0438 - GPL. \u0420\u0435\u0430\u043B\u0438\u0437\u0430\u0446\u0438\u044F \u0441\u0438\u0441\u0442\u0435\u043C\u044B-\u043D\u0430-\u043A\u0440\u0438\u0441\u0442\u0430\u043B\u043B\u0435 \u0441 OpenRISC 1200 \u043D\u0430\u0437\u044B\u0432\u0430\u0435\u0442\u0441\u044F ORPSoC (OpenRISC Reference Platform System-on-Chip). \u0420\u0430\u0431\u043E\u0442\u043E\u0441\u043F\u043E\u0441\u043E\u0431\u043D\u043E\u0441\u0442\u044C ORPSoC \u0438 \u0434\u0440\u0443\u0433\u0438\u0445 \u0432\u0430\u0440\u0438\u0430\u043D\u0442\u043E\u0432 OR1200 \u0431\u044B\u043B\u0430 \u043F\u0440\u043E\u0434\u0435\u043C\u043E\u043D\u0441\u0442\u0440\u0438\u0440\u043E\u0432\u0430\u043D\u0430 \u043D\u0430 FPGA. \u041D\u0430 OpenRISC \u043F\u043E\u0440\u0442\u0438\u0440\u043E\u0432\u0430\u043D \u043D\u0430\u0431\u043E\u0440 \u0438\u043D\u0441\u0442\u0440\u0443\u043C\u0435\u043D\u0442\u043E\u0432 \u0434\u043B\u044F \u0440\u0430\u0437\u0440\u0430\u0431\u043E\u0442\u043A\u0438 GNU toolchain, \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u044E\u0449\u0438\u0439 \u043D\u0435\u0441\u043A\u043E\u043B\u044C\u043A\u043E \u044F\u0437\u044B\u043A\u043E\u0432 \u043F\u0440\u043E\u0433\u0440\u0430\u043C\u043C\u0438\u0440\u043E\u0432\u0430\u043D\u0438\u044F, \u0442\u0430\u043A\u0436\u0435 Linux \u0438 \u03BCClinux. OpenRISC \u043F\u043E\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442\u0441\u044F \u044F\u0434\u0440\u043E\u043C linux \u043D\u0430\u0447\u0438\u043D\u0430\u044F \u0441 \u0432\u0435\u0440\u0441\u0438\u0438 3.1."@ru . . . . . . . . . . . "OpenRISC \u00E8 un progetto di hardware libero di un microprocessore RISC sviluppato da OpenCores e rilasciato sotto GNU Lesser General Public License. Il processore \u00E8 descritto con il linguaggio Verilog ed \u00E8 sintetizzabile su ASIC o su FPGA. Il \u00E8 stato portato sull'ambiente OpenRISC e gli ambienti di sviluppo di molti linguaggi sono stati resi disponibile per la piattaforma. I sistemi operativi Linux e \u03BCClinux sono disponibili per il processore."@it . "OpenRISC ist ein Projekt der -Entwickler-Community. Das Ziel des Projekts ist die Entwicklung einer hochkonfigurierbaren RISC-CPU als Open Hardware. Die bisher einzige fertiggestellte Architektur ist die OpenRISC-1000-Familie (kurz OR1k), die als 32- und 64-Bit-Version verf\u00FCgbar ist.Das Design des OpenRISC 1200 (kurz OR1200) war das erste, das in der Hardwarebeschreibungssprache Verilog unter der GNU Lesser General Public License (GNU LGPL) ver\u00F6ffentlicht wurde. Die Firmware und der Microcode zum Prozessor wurden unter der GNU General Public License (GNU GPL) bereitgestellt. Basierend auf dem OpenRISC 1200 wurde eine System-on-a-Chip-Variante mit der Bezeichnung ORPSoC (= OpenRISC Reference Platform System-on-Chip) entwickelt. Auf beiden Varianten wurde der Betrieb eines Linux-Systems erfolgreich getestet. Dazu wurden die Prozessoren in einem FPGA implementiert."@de . . . . "Yes , hence royalty free"@en . . . . "OpenRISC"@ca . . . . . . . . . . . . . . . . . . . . . . . . "OpenRISC"@es . "OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community. The first (and as of 2019 only) architectural description is for the OpenRISC 1000 (\"OR1k\"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support.The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL).The later mor1kx implementation, which has some advantages compared to the OR 1200, was designed by Julius Baxter and is also written in Verilog.Additionally software simulators exist, which implement the OR1k specification. The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL). A reference system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs), and there have been several commercial derivatives produced. Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC."@en . . . "Fixed"@en . "OpenRISC"@it . . "OpenRISC"@ja . . . . "OpenRISC"@de . . "OpenRISC"@en . . . . . . . . . . "OpenRISC\u306FOpenCores\u30B3\u30DF\u30E5\u30CB\u30C6\u30A3\u306E\u5143\u3005\u306E\u65D7\u8266\u30D7\u30ED\u30B8\u30A7\u30AF\u30C8\u3067\u3042\u308B\u3002\u3053\u306E\u30D7\u30ED\u30B8\u30A7\u30AF\u30C8\u306E\u76EE\u7684\u306F\u3001\u4E00\u9023\u306E\u6C4E\u7528\u306E\u30AA\u30FC\u30D7\u30F3\u30BD\u30FC\u30B9\u306ERISC CPU\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u3092\u958B\u767A\u3059\u308B\u3053\u3068\u3067\u3042\u308B\u3002\u6700\u521D\u3067\u73FE\u5728\u306E\u3068\u3053\u308D\u552F\u4E00\u306E\u30A2\u30FC\u30AD\u30C6\u30AF\u30C1\u30E3\u306F\u3001OpenRISC 1000\u3067\u3042\u308B\u3002\u3053\u308C\u306F\u3001 32\u30D3\u30C3\u30C8\u306864\u30D3\u30C3\u30C8\u304C\u3042\u308A\u3001\u30AA\u30D7\u30B7\u30E7\u30F3\u3068\u3057\u3066\u6D6E\u52D5\u5C0F\u6570\u70B9\u6F14\u7B97\u3068\u30D9\u30AF\u30C8\u30EB\u6F14\u7B97\u3092\u6301\u3064\u30D5\u30A1\u30DF\u30EA\u3067\u3042\u308B\u3002 OpenCores\u306E\u30C1\u30FC\u30E0\u306F\u6700\u521D\u306E\u5B9F\u88C5\u3067\u3042\u308B\u3092\u63D0\u4F9B\u3057\u3066\u3044\u308B\u3002\u3053\u308C\u306FVerilog\u30CF\u30FC\u30C9\u30A6\u30A7\u30A2\u8A18\u8FF0\u8A00\u8A9E\u3067\u66F8\u304B\u308C\u3066\u3044\u308B\u3002\u30CF\u30FC\u30C9\u30A6\u30A7\u30A2\u306E\u30C7\u30B6\u30A4\u30F3\u306F\u3001GNU Lesser General Public License\u3067\u30EA\u30EA\u30FC\u30B9\u3055\u308C\u305F\u304C\u3001\u30E2\u30C7\u30EB\u3068\u30D5\u30A1\u30FC\u30E0\u30A6\u30A7\u30A2\u306FGNU General Public License\u3067\u30EA\u30EA\u30FC\u30B9\u3055\u308C\u305F\u3002\u30EA\u30D5\u30A1\u30EC\u30F3\u30B9\u306ESoC\u306E\u5B9F\u88C5\u306FOpenRISC 1200\u30D9\u30FC\u30B9\u3067\u958B\u767A\u3055\u308C\u3001ORPSoC (the OpenRISC Reference Platform System-on-Chip)\u3068\u3057\u3066\u77E5\u3089\u308C\u3066\u3044\u308B\u3002ORPSoC\u3084\u4ED6\u306EOpenRISC 1200\u30D9\u30FC\u30B9\u306E\u30C7\u30B6\u30A4\u30F3\u306E\u30C7\u30E2\u30F3\u30B9\u30C8\u30EC\u30FC\u30B7\u30E7\u30F3\u3092\u3057\u305F\u30B0\u30EB\u30FC\u30D7\u306F\u3001FPGA\u4E0A\u3067\u52D5\u304B\u3057\u3066\u3044\u305F\u3002."@ja . . . "OpenRISC \u00E8 un progetto di hardware libero di un microprocessore RISC sviluppato da OpenCores e rilasciato sotto GNU Lesser General Public License. Il processore \u00E8 descritto con il linguaggio Verilog ed \u00E8 sintetizzabile su ASIC o su FPGA. Il \u00E8 stato portato sull'ambiente OpenRISC e gli ambienti di sviluppo di molti linguaggi sono stati resi disponibile per la piattaforma. I sistemi operativi Linux e \u03BCClinux sono disponibili per il processore."@it . . . . "OpenRISC est le projet phare originel de la communaut\u00E9 (en). Il a pour but de d\u00E9velopper une s\u00E9rie d'architectures CPU RISC open source \u00E0 usage g\u00E9n\u00E9ral. La premi\u00E8re (et jusqu'\u00E0 maintenant l'unique) description d'architecture publi\u00E9e est celle de l'OpenRISC 1000, d\u00E9crivant une famille de processeurs 32 et 64 bits avec en option le support de la virgule flottante et des vecteurs."@fr .