. "SSE3 (conosciuto anche con il nome di Prescott New Instructions o PNI) \u00E8 un instruction set SIMD dell'architettura IA-32, sviluppato da Intel, che estende la precedente versione (SSE2). I primi set SIMD sulle piattaforme x86 sono stati l'MMX, e il 3DNow! (usato solo da parte di AMD), e successivamente SSE e SSE2. Intel ha introdotto le istruzioni SSE3 agli inizi del 2004 con il Pentium 4 basato sul core Prescott, mentre AMD ha provveduto a implementarne il supporto nei suoi Athlon 64, attraverso la \"revision\" E, solo nell'aprile 2005."@it . . . "SSE3"@uk . . . . "4499"^^ . . "SSE3"@fr . "SSE3\uFF08Streaming SIMD Extensions 3\uFF09\uFF0C\u53C8\u7A31PNI\uFF08Prescott New Instructions\uFF09\uFF0C\u5B83\u6307\u7684\u662F\uFF1A\u5728\u539F\u6709\u67B6\u69CB\u7684\u8655\u7406\u5668\u4E2D\uFF0C\u6240\u7B2C\u4E09\u6B21\u984D\u5916\u65B0\u589E\u3001\u6DFB\u52A0\u7684\u591A\u5A92\u9AD4\u6307\u4EE4\u96C6\uFF0C\u4E4B\u524D\u7684\u5169\u6B21\u5206\u5225\u662FSSE\u3001SSE2\u3002 SSE3\u662FIntel\u516C\u53F8\u6240\u5176\u539F\u6709IA-32\u67B6\u69CB\u7684\u8655\u7406\u5668\u6240\u7814\u5275\uFF0C\u4E26\u57282004\u5E74\u521D\u7684\u65B0\u6B3EPentium 4\uFF08P4E,Prescott\u6838\u5FC3\uFF09\u8655\u7406\u5668\u4E2D\u4F7F\u7528\uFF0C\u4E4B\u5F8C2005\u5E744\u6708AMD\u516C\u53F8\u4E5F\u767C\u8868\u5177\u5099\u90E8\u5206SSE3\u529F\u6548\u7684\u8655\u7406\u5668\uFF1AAthlon 64\uFF08E3\u6B65\u9032\u6838\u5FC3\uFF09\uFF0C\u6B64\u5F8C\u7684x86\u8655\u7406\u5668\u4E5F\u5E7E\u4E4E\u90FD\u5177\u5099SSE3\u7684\u65B0\u6307\u4EE4\u96C6\u529F\u80FD\u3002 \u6B64\u5916\uFF0C\u5728SSE3\u63D0\u51FA\u4E4B\u524D\uFF0Cx86\u67B6\u69CB\u7684\u8655\u7406\u5668\u5148\u5F8C\u5DF2\u6709\u591A\u7A2E\u591A\u5A92\u9AD4\u6307\u4EE4\u96C6\u88AB\u63D0\u5275\u8207\u4F7F\u7528\uFF0C\u5148\u5F8C\u9806\u5E8F\u5927\u81F4\u662FIntel MMX\u3001AMD 3DNow!\u3001Intel SSE\u3001Intel SSE2\u7B49\u3002 \u9644\u5E36\u4E00\u63D0\u7684\u662F\uFF0CSSE3\u6BD4\u5728\u5B83\u4E4B\u524D\u7684SSE2\u589E\u52A013\u689D\u65B0\u6307\u4EE4\u3002"@zh . "SSE3 (PNI \u2014 Prescott New Instruction) \u2014 \u0442\u0440\u0435\u0442\u044C\u044F \u0432\u0435\u0440\u0441\u0438\u044F SIMD-\u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043D\u0438\u044F Intel, \u043F\u043E\u0442\u043E\u043C\u043E\u043A SSE, SSE2 \u0438 MMX. \u0412\u043F\u0435\u0440\u0432\u044B\u0435 \u043F\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043B\u0435\u043D\u043E 2 \u0444\u0435\u0432\u0440\u0430\u043B\u044F 2004 \u0433\u043E\u0434\u0430 \u0432 \u044F\u0434\u0440\u0435 Prescott \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0430 Pentium 4. \u0412 2005 AMD \u043F\u0440\u0435\u0434\u043B\u043E\u0436\u0438\u043B\u0430 \u0441\u0432\u043E\u044E \u0440\u0435\u0430\u043B\u0438\u0437\u0430\u0446\u0438\u044E SSE3 \u0434\u043B\u044F \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 Athlon 64 (\u044F\u0434\u0440\u0430 Venice, San Diego \u0438 Newark). \u041D\u0430\u0431\u043E\u0440 SSE3 \u0441\u043E\u0434\u0435\u0440\u0436\u0438\u0442 13 \u0438\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0438\u0439: FISTTP (x87), MOVSLDUP (SSE), MOVSHDUP (SSE), MOVDDUP (SSE2), LDDQU (SSE/SSE2), ADDSUBPD (SSE), ADDSUBPD (SSE2), HADDPS (SSE), HSUBPS (SSE), HADDPD (SSE2), HSUBPD (SSE2), MONITOR (\u043D\u0435\u0442 \u0430\u043D\u0430\u043B\u043E\u0433\u0430 \u0432 SSE3 \u0434\u043B\u044F AMD), MWAIT (\u043D\u0435\u0442 \u0430\u043D\u0430\u043B\u043E\u0433\u0430 \u0432 SSE3 \u0434\u043B\u044F AMD). \u041D\u0430\u0438\u0431\u043E\u043B\u0435\u0435 \u0437\u0430\u043C\u0435\u0442\u043D\u043E\u0435 \u0438\u0437\u043C\u0435\u043D\u0435\u043D\u0438\u0435 \u2014 \u0432\u043E\u0437\u043C\u043E\u0436\u043D\u043E\u0441\u0442\u044C \u0433\u043E\u0440\u0438\u0437\u043E\u043D\u0442\u0430\u043B\u044C\u043D\u043E\u0439 \u0440\u0430\u0431\u043E\u0442\u044B \u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430\u043C\u0438. \u0415\u0441\u043B\u0438 \u0433\u043E\u0432\u043E\u0440\u0438\u0442\u044C \u0431\u043E\u043B\u0435\u0435 \u043A\u043E\u043D\u043A\u0440\u0435\u0442\u043D\u043E, \u0434\u043E\u0431\u0430\u0432\u043B\u0435\u043D\u044B \u043A\u043E\u043C\u0430\u043D\u0434\u044B \u0441\u043B\u043E\u0436\u0435\u043D\u0438\u044F \u0438 \u0432\u044B\u0447\u0438\u0442\u0430\u043D\u0438\u044F \u043D\u0435\u0441\u043A\u043E\u043B\u044C\u043A\u0438\u0445 \u0437\u043D\u0430\u0447\u0435\u043D\u0438\u0439, \u0445\u0440\u0430\u043D\u044F\u0449\u0438\u0445\u0441\u044F \u0432 \u043E\u0434\u043D\u043E\u043C \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0435. \u042D\u0442\u0438 \u043A\u043E\u043C\u0430\u043D\u0434\u044B \u0443\u043F\u0440\u043E\u0441\u0442\u0438\u043B\u0438 \u0440\u044F\u0434 DSP- \u0438 3D-\u043E\u043F\u0435\u0440\u0430\u0446\u0438\u0439.\u0421\u0443\u0449\u0435\u0441\u0442\u0432\u0443\u0435\u0442 \u0442\u0430\u043A\u0436\u0435 \u043D\u043E\u0432\u0430\u044F \u043A\u043E\u043C\u0430\u043D\u0434\u0430 \u0434\u043B\u044F \u043F\u0440\u0435\u043E\u0431\u0440\u0430\u0437\u043E\u0432\u0430\u043D\u0438\u044F \u0437\u043D\u0430\u0447\u0435\u043D\u0438\u0439 \u0441 \u043F\u043B\u0430\u0432\u0430\u044E\u0449\u0435\u0439 \u0442\u043E\u0447\u043A\u043E\u0439 \u0432 \u0446\u0435\u043B\u044B\u0435 \u0431\u0435\u0437 \u043D\u0435\u043E\u0431\u0445\u043E\u0434\u0438\u043C\u043E\u0441\u0442\u0438 \u0432\u043D\u043E\u0441\u0438\u0442\u044C \u0438\u0437\u043C\u0435\u043D\u0435\u043D\u0438\u044F \u0432 \u0433\u043B\u043E\u0431\u0430\u043B\u044C\u043D\u043E\u043C \u0440\u0435\u0436\u0438\u043C\u0435 \u043E\u043A\u0440\u0443\u0433\u043B\u0435\u043D\u0438\u044F. Google Chrome \u043D\u0430\u0447\u0438\u043D\u0430\u044F \u0441 \u0432\u0435\u0440\u0441\u0438\u0438 89 \u0442\u0440\u0435\u0431\u0443\u0435\u0442 \u043D\u0430\u043B\u0438\u0447\u0438\u044F \u044D\u0442\u0438\u0445 \u0438\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0438\u0439"@ru . . "SSE3 Conocido por el nombre en c\u00F3digo que le puso Intel, Prescott New Instructions (PNI) es la tercera generaci\u00F3n de las instrucciones SSE para la arquitectura IA-32. Intel mostr\u00F3 las SSE3 a principios de 2004 con la revisi\u00F3n de su CPU Pentium 4 llamada Prescott. En abril de 2005 AMD sac\u00F3 una parte del SSE3 en la revisi\u00F3n E (llamadas Venice y San Diego) de su CPU Athlon 64. SSE3 a\u00F1ade 13 nuevas instrucciones a SSE2."@es . "SSE3 (\u0430\u043D\u0433\u043B. Streaming SIMD Extensions 3, \u043F\u043E\u0442\u043E\u043A\u043E\u0432\u0435 SIMD-\u0440\u043E\u0437\u0448\u0438\u0440\u0435\u043D\u043D\u044F \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430, \u0442\u0430\u043A\u043E\u0436 \u0432\u0456\u0434\u043E\u043C\u0435 \u044F\u043A PNI(Prescott New Instruction)) \u2014 \u0446\u0435 SIMD (\u0430\u043D\u0433\u043B. Single Instruction, Multiple Data, \u041E\u0434\u043D\u0430 \u0456\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0456\u044F \u2014 \u0431\u0430\u0433\u0430\u0442\u043E \u0434\u0430\u043D\u0438\u0445) \u043D\u0430\u0431\u0456\u0440 \u0456\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0456\u0439, \u0440\u043E\u0437\u0440\u043E\u0431\u043B\u0435\u043D\u0438\u0445 Intel, \u0456 \u043F\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043B\u0435\u043D\u0438\u0445 2 \u043B\u044E\u0442\u043E\u0433\u043E 2004 \u0440\u043E\u043A\u0443 \u0443 \u044F\u0434\u0440\u0456 Prescott \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430 Pentium 4. \u0423 2005 AMD \u043F\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u0438\u043B\u0430 \u0441\u0432\u043E\u044E \u0440\u0435\u0430\u043B\u0456\u0437\u0430\u0446\u0456\u044E SSE3 \u0434\u043B\u044F \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0456\u0432 Athlon 64. \u041D\u0430\u0431\u0456\u0440 SSE3 \u043C\u0456\u0441\u0442\u0438\u0442\u044C 13 \u0456\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0456\u0439: FISTTP (x87), MOVSLDUP (SSE), MOVSHDUP (SSE), MOVDDUP (SSE2), LDDQU (SSE/SSE2), ADDSUBPD (SSE), ADDSUBPD (SSE2), HADDPS (SSE), HSUBPS (SSE), HADDPD (SSE2), HSUBPD (SSE2), MONITOR (\u0430\u043D\u0430\u043B\u043E\u0433\u0430 \u0443 \u0440\u0435\u0430\u043B\u0456\u0437\u0430\u0446\u0456\u0457 SSE3 \u0432\u0456\u0434 AMD \u043D\u0435\u043C\u0430\u0454), MWAIT (\u0442\u0430\u043A\u043E\u0436 \u0432\u0456\u0434\u0441\u0443\u0442\u043D\u0456\u0439 \u0443 \u0440\u0435\u0430\u043B\u0456\u0437\u0430\u0446\u0456\u0457 SSE3 \u0432\u0456\u0434 AMD)."@uk . . . "SSE3, connu aussi par son nom de code interne Prescott New Instructions (PNI), est la troisi\u00E8me g\u00E9n\u00E9ration du jeu d'instructions SSE pour l'architecture IA-32. Intel a introduit SSE3 au d\u00E9but de l'ann\u00E9e 2004 avec la version Prescott de son processeur Pentium 4. En avril 2005, AMD a introduit un sous-ensemble de SSE3 dans la r\u00E9vision E de leur processeur Athlon 64 (Venice et San Diego). Leur jeu d'instructions SIMD pour la plate-forme x86, du plus ancien au plus r\u00E9cent, sont MMX, 3DNow! (d\u00E9velopp\u00E9 par AMD), SSE et SSE2."@fr . . . . . . "SSE3 (conosciuto anche con il nome di Prescott New Instructions o PNI) \u00E8 un instruction set SIMD dell'architettura IA-32, sviluppato da Intel, che estende la precedente versione (SSE2). I primi set SIMD sulle piattaforme x86 sono stati l'MMX, e il 3DNow! (usato solo da parte di AMD), e successivamente SSE e SSE2. Intel ha introdotto le istruzioni SSE3 agli inizi del 2004 con il Pentium 4 basato sul core Prescott, mentre AMD ha provveduto a implementarne il supporto nei suoi Athlon 64, attraverso la \"revision\" E, solo nell'aprile 2005. Il set SSE3 originale aggiunge 13 nuove istruzioni rispetto al predecessore SSE2; la pi\u00F9 rivoluzionaria di queste istruzioni consente di lavorare orizzontalmente in un registro in contrapposizione con quanto avveniva precedentemente in cui era possibile solo verticalmente. Pi\u00F9 precisamente, sono state aggiunte le istruzioni per sommare e sottrarre i molteplici valori memorizzati in un singolo registro. Tali istruzioni semplificano l'implementazione di un gran numero di operazioni DSP e 3D. \u00C8 inoltre presente una nuova istruzione per convertire i numeri a virgola mobile in interi senza interferire con il normale flusso dell'elaborazione della CPU, quindi senza creare stalli nella pipeline. Nel 2006, con il lancio dell'architettura Intel Core Microarchitecture \u00E8 stata lanciata sul mercato un'evoluzione del set SSE3, chiamato SSSE3 che aggiunge altre 32 istruzioni e ottimizza una serie di aspetti del set originale."@it . . . . . "1112081396"^^ . . "SSE3\uFF08Streaming SIMD Extensions 3\uFF09\uFF0C\u53C8\u7A31PNI\uFF08Prescott New Instructions\uFF09\uFF0C\u5B83\u6307\u7684\u662F\uFF1A\u5728\u539F\u6709\u67B6\u69CB\u7684\u8655\u7406\u5668\u4E2D\uFF0C\u6240\u7B2C\u4E09\u6B21\u984D\u5916\u65B0\u589E\u3001\u6DFB\u52A0\u7684\u591A\u5A92\u9AD4\u6307\u4EE4\u96C6\uFF0C\u4E4B\u524D\u7684\u5169\u6B21\u5206\u5225\u662FSSE\u3001SSE2\u3002 SSE3\u662FIntel\u516C\u53F8\u6240\u5176\u539F\u6709IA-32\u67B6\u69CB\u7684\u8655\u7406\u5668\u6240\u7814\u5275\uFF0C\u4E26\u57282004\u5E74\u521D\u7684\u65B0\u6B3EPentium 4\uFF08P4E,Prescott\u6838\u5FC3\uFF09\u8655\u7406\u5668\u4E2D\u4F7F\u7528\uFF0C\u4E4B\u5F8C2005\u5E744\u6708AMD\u516C\u53F8\u4E5F\u767C\u8868\u5177\u5099\u90E8\u5206SSE3\u529F\u6548\u7684\u8655\u7406\u5668\uFF1AAthlon 64\uFF08E3\u6B65\u9032\u6838\u5FC3\uFF09\uFF0C\u6B64\u5F8C\u7684x86\u8655\u7406\u5668\u4E5F\u5E7E\u4E4E\u90FD\u5177\u5099SSE3\u7684\u65B0\u6307\u4EE4\u96C6\u529F\u80FD\u3002 \u6B64\u5916\uFF0C\u5728SSE3\u63D0\u51FA\u4E4B\u524D\uFF0Cx86\u67B6\u69CB\u7684\u8655\u7406\u5668\u5148\u5F8C\u5DF2\u6709\u591A\u7A2E\u591A\u5A92\u9AD4\u6307\u4EE4\u96C6\u88AB\u63D0\u5275\u8207\u4F7F\u7528\uFF0C\u5148\u5F8C\u9806\u5E8F\u5927\u81F4\u662FIntel MMX\u3001AMD 3DNow!\u3001Intel SSE\u3001Intel SSE2\u7B49\u3002 \u9644\u5E36\u4E00\u63D0\u7684\u662F\uFF0CSSE3\u6BD4\u5728\u5B83\u4E4B\u524D\u7684SSE2\u589E\u52A013\u689D\u65B0\u6307\u4EE4\u3002"@zh . . . . . . "SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD, but not supported by Intel processors), SSE, and SSE2. SSE3 contains 13 new instructions over SSE2."@en . . . . "\uC778\uD154 \uCF54\uB4DC\uC774\uB984 \uD504\uB808\uC2A4\uCE87 \uC2E0\uADDC \uBA85\uB839\uC5B4(Prescott New Instructions)\uB85C \uC54C\uB824\uC9C4 SSE3\uB294 IA-32\uC6A9 3\uBC88\uC9F8 SSE\uBA85\uB839\uC5B4 \uC9D1\uD569\uC774\uB2E4. \uC778\uD154\uC740 SSE3\uB97C \uD39C\uD2F0\uC5C4 4 CPU\uC778 \uD504\uB808\uC2A4\uCE87\uACFC \uD568\uAED8 2004\uB144 \uCD08\uC5D0 \uBC1C\uD45C\uB97C \uD558\uC600\uB2E4. 2005\uB144 4\uC6D4\uC5D0 AMD\uB294 \uC560\uC2AC\uB860 64 CPU\uC758 \uBC84\uC804 E(\uBCA0\uB2C8\uC2A4\uC640 \uC0CC \uB514\uC5D0\uACE0)\uC5D0\uC11C SSE3\uC758 \uC77C\uBD80\uB97C \uBC1C\uD45C\uD558\uC600\uB2E4. x86\uD50C\uB7AB\uD3FC\uC5D0\uC11C\uC758 \uC774\uC804 SIMD\uBA85\uB839\uC5B4 \uC9D1\uD569\uC740 \uC2DC\uAC04\uC21C\uC73C\uB85C MMX (\uBA85\uB839\uC5B4 \uC9D1\uD569), 3DNow! (AMD\uC5D0 \uC758\uD574 \uAC1C\uBC1C), SSE \uADF8\uB9AC\uACE0 SSE2\uC774\uB2E4. SSE3\uB294 SSE2\uB300\uBE44 13\uAC1C\uC758 \uC0C8\uB85C\uC6B4 \uBA85\uB839\uC5B4\uAC00 \uD3EC\uD568\uB418\uC5B4 \uC788\uB2E4."@ko . . "De SSE3 uitbreiding op de IA-32 SSE2 instructieset is door Intel ontwikkeld en begin 2004 voor het eerst gebruikt in de Prescott herziening van de Pentium 4 processor van dit bedrijf. AMD introduceerde later een subset van SSE3 in revisie E (Veneti\u00EB en San Diego) van hun Athlon processoren. De meest opvallende verandering ten opzichte van SSE2 is de mogelijkheid om horizontaal te werken in een register, in tegenstelling tot de strikt verticale werking van alle voorgaande SSE-instructies. Instructies om op te tellen en af te trekken van meerdere waarden die zijn opgeslagen in een enkel register zijn toegevoegd. Deze instructies vereenvoudigen de uitvoering van een aantal DSP en 3D operaties."@nl . . . "SSE3 (PNI \u2014 Prescott New Instruction) \u2014 \u0442\u0440\u0435\u0442\u044C\u044F \u0432\u0435\u0440\u0441\u0438\u044F SIMD-\u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043D\u0438\u044F Intel, \u043F\u043E\u0442\u043E\u043C\u043E\u043A SSE, SSE2 \u0438 MMX. \u0412\u043F\u0435\u0440\u0432\u044B\u0435 \u043F\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043B\u0435\u043D\u043E 2 \u0444\u0435\u0432\u0440\u0430\u043B\u044F 2004 \u0433\u043E\u0434\u0430 \u0432 \u044F\u0434\u0440\u0435 Prescott \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u0430 Pentium 4. \u0412 2005 AMD \u043F\u0440\u0435\u0434\u043B\u043E\u0436\u0438\u043B\u0430 \u0441\u0432\u043E\u044E \u0440\u0435\u0430\u043B\u0438\u0437\u0430\u0446\u0438\u044E SSE3 \u0434\u043B\u044F \u043F\u0440\u043E\u0446\u0435\u0441\u0441\u043E\u0440\u043E\u0432 Athlon 64 (\u044F\u0434\u0440\u0430 Venice, San Diego \u0438 Newark). \u041D\u0430\u0431\u043E\u0440 SSE3 \u0441\u043E\u0434\u0435\u0440\u0436\u0438\u0442 13 \u0438\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0438\u0439: FISTTP (x87), MOVSLDUP (SSE), MOVSHDUP (SSE), MOVDDUP (SSE2), LDDQU (SSE/SSE2), ADDSUBPD (SSE), ADDSUBPD (SSE2), HADDPS (SSE), HSUBPS (SSE), HADDPD (SSE2), HSUBPD (SSE2), MONITOR (\u043D\u0435\u0442 \u0430\u043D\u0430\u043B\u043E\u0433\u0430 \u0432 SSE3 \u0434\u043B\u044F AMD), MWAIT (\u043D\u0435\u0442 \u0430\u043D\u0430\u043B\u043E\u0433\u0430 \u0432 SSE3 \u0434\u043B\u044F AMD)."@ru . "494502"^^ . . . . . . . . . "SSE3"@nl . . "SSE3"@pl . "Streaming SIMD Extensions 3 (SSE3, oznaczany r\u00F3wnie\u017C przez firm\u0119 Intel jako Prescott New Instructions lub PNI) \u2013 zestaw instrukcji SIMD wykorzystywany w architekturze IA-32. Wcze\u015Bniejsze zestawy SIMD stosowane na platformie x86, od najstarszej to: MMX, 3DNow! (u\u017Cywany tylko przez AMD), SSE i SSE2. SSE3 wprowadza 13 nowych rozkaz\u00F3w w stosunku do swojego poprzednika SSE2, s\u0105 to: Intel wprowadzi\u0142 SSE3 2 lutego 2004 roku wraz z procesorem Pentium 4 Prescott, natomiast firma AMD w procesorach Athlon 64 od wersji E."@pl . . "\uC778\uD154 \uCF54\uB4DC\uC774\uB984 \uD504\uB808\uC2A4\uCE87 \uC2E0\uADDC \uBA85\uB839\uC5B4(Prescott New Instructions)\uB85C \uC54C\uB824\uC9C4 SSE3\uB294 IA-32\uC6A9 3\uBC88\uC9F8 SSE\uBA85\uB839\uC5B4 \uC9D1\uD569\uC774\uB2E4. \uC778\uD154\uC740 SSE3\uB97C \uD39C\uD2F0\uC5C4 4 CPU\uC778 \uD504\uB808\uC2A4\uCE87\uACFC \uD568\uAED8 2004\uB144 \uCD08\uC5D0 \uBC1C\uD45C\uB97C \uD558\uC600\uB2E4. 2005\uB144 4\uC6D4\uC5D0 AMD\uB294 \uC560\uC2AC\uB860 64 CPU\uC758 \uBC84\uC804 E(\uBCA0\uB2C8\uC2A4\uC640 \uC0CC \uB514\uC5D0\uACE0)\uC5D0\uC11C SSE3\uC758 \uC77C\uBD80\uB97C \uBC1C\uD45C\uD558\uC600\uB2E4. x86\uD50C\uB7AB\uD3FC\uC5D0\uC11C\uC758 \uC774\uC804 SIMD\uBA85\uB839\uC5B4 \uC9D1\uD569\uC740 \uC2DC\uAC04\uC21C\uC73C\uB85C MMX (\uBA85\uB839\uC5B4 \uC9D1\uD569), 3DNow! (AMD\uC5D0 \uC758\uD574 \uAC1C\uBC1C), SSE \uADF8\uB9AC\uACE0 SSE2\uC774\uB2E4. SSE3\uB294 SSE2\uB300\uBE44 13\uAC1C\uC758 \uC0C8\uB85C\uC6B4 \uBA85\uB839\uC5B4\uAC00 \uD3EC\uD568\uB418\uC5B4 \uC788\uB2E4."@ko . "SSE3"@ru . . . . . . . . . . "Die Streaming SIMD Extensions 3 (kurz SSE3) ist die zweite Erweiterung des SSE-Befehlssatzes. Sie ist auch unter dem Intel-Codenamen Prescott New Instructions (PNI) bekannt, da sie zuerst bei der Prescott-Variante des Pentium 4 ab Fr\u00FChjahr 2004 verwendet wurde. AMD unterst\u00FCtzt diese Erweiterungen seit April 2005 und f\u00FChrte diese mit den E-Steppings beim Athlon 64, Opteron und Sempron ein. VIA bzw. Centaur unterst\u00FCtzen mit dem C7 ebenfalls die neuen Befehle. SSE3 ist eine erneute Erweiterung des SIMD-Befehlssatzes f\u00FCr die x86-Architektur (genauer die IA-32-Prozessorarchitektur). Die vorherigen Erweiterungen waren MMX, 3DNow, SSE und SSE2. SSE3 erweitert den SSE2-Befehlssatz um 13 neue Instruktionen: \n* fisttp zur Wandelung von Gleitkommazahlen in ganze Zahlen \n* addsubps, addsubpd, movsldup, movshdup, movddup f\u00FCr komplexe Arithmetik \n* lddqu zur Video-Kodierung \n* haddps, hsubps, haddpd, hsubpd zur Unterst\u00FCtzung der Grafik-Aufbereitung \n* monitor, mwait zur Thread-Kommunikation Die Unterst\u00FCtzung der letzten beiden Befehle muss mittels CPUID-Instruktion explizit gepr\u00FCft werden, da sie Mehrkernprozessoren bzw. Hyper-Threading f\u00E4hige CPUs voraussetzen. Die auff\u00E4lligste Erweiterung ist die Erm\u00F6glichung von horizontaler Addition und Subtraktion in einem Register, die schon bei 3DNow m\u00F6glich war. Dies vereinfacht die Programmierung von DSP- und 3D-Funktionen, w\u00E4hrend in den vorhergehenden SSE-Versionen mehr oder weniger nur vertikale Operationen m\u00F6glich waren."@de . . "Streaming SIMD Extensions 3 (SSE3, oznaczany r\u00F3wnie\u017C przez firm\u0119 Intel jako Prescott New Instructions lub PNI) \u2013 zestaw instrukcji SIMD wykorzystywany w architekturze IA-32. Wcze\u015Bniejsze zestawy SIMD stosowane na platformie x86, od najstarszej to: MMX, 3DNow! (u\u017Cywany tylko przez AMD), SSE i SSE2. SSE3 wprowadza 13 nowych rozkaz\u00F3w w stosunku do swojego poprzednika SSE2, s\u0105 to: \n* FISTTP \u2013 do konwersji liczb zmiennoprzecinkowych do ca\u0142kowitych \n* ADDSUBPS, ADDSUBPD, MOVSLDUP, MOVSHDUP, MOVDDUP \u2013 do arytmetyki zespolonej \n* LDDQU \u2013 do kodowania wideo \n* HADDPS, HSUBPS, HADDPD, HSUBPD \u2013 do grafiki (SIMD FP/AOS) \n* MONITOR, MWAIT \u2013 do synchronizacji w\u0105tk\u00F3w Intel wprowadzi\u0142 SSE3 2 lutego 2004 roku wraz z procesorem Pentium 4 Prescott, natomiast firma AMD w procesorach Athlon 64 od wersji E."@pl . . . . . . . . . . . "SSE3"@en . . . "SSE3"@es . "Streaming SIMD Extensions 3"@de . . "SSE3"@it . . "SSE3"@ko . . . . . "SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD, but not supported by Intel processors), SSE, and SSE2. SSE3 contains 13 new instructions over SSE2."@en . . . "SSE3 (\u0430\u043D\u0433\u043B. Streaming SIMD Extensions 3, \u043F\u043E\u0442\u043E\u043A\u043E\u0432\u0435 SIMD-\u0440\u043E\u0437\u0448\u0438\u0440\u0435\u043D\u043D\u044F \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430, \u0442\u0430\u043A\u043E\u0436 \u0432\u0456\u0434\u043E\u043C\u0435 \u044F\u043A PNI(Prescott New Instruction)) \u2014 \u0446\u0435 SIMD (\u0430\u043D\u0433\u043B. Single Instruction, Multiple Data, \u041E\u0434\u043D\u0430 \u0456\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0456\u044F \u2014 \u0431\u0430\u0433\u0430\u0442\u043E \u0434\u0430\u043D\u0438\u0445) \u043D\u0430\u0431\u0456\u0440 \u0456\u043D\u0441\u0442\u0440\u0443\u043A\u0446\u0456\u0439, \u0440\u043E\u0437\u0440\u043E\u0431\u043B\u0435\u043D\u0438\u0445 Intel, \u0456 \u043F\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043B\u0435\u043D\u0438\u0445 2 \u043B\u044E\u0442\u043E\u0433\u043E 2004 \u0440\u043E\u043A\u0443 \u0443 \u044F\u0434\u0440\u0456 Prescott \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0430 Pentium 4. \u0423 2005 AMD \u043F\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u0438\u043B\u0430 \u0441\u0432\u043E\u044E \u0440\u0435\u0430\u043B\u0456\u0437\u0430\u0446\u0456\u044E SSE3 \u0434\u043B\u044F \u043F\u0440\u043E\u0446\u0435\u0441\u043E\u0440\u0456\u0432 Athlon 64."@uk . . "De SSE3 uitbreiding op de IA-32 SSE2 instructieset is door Intel ontwikkeld en begin 2004 voor het eerst gebruikt in de Prescott herziening van de Pentium 4 processor van dit bedrijf. AMD introduceerde later een subset van SSE3 in revisie E (Veneti\u00EB en San Diego) van hun Athlon processoren."@nl . "SSE3, connu aussi par son nom de code interne Prescott New Instructions (PNI), est la troisi\u00E8me g\u00E9n\u00E9ration du jeu d'instructions SSE pour l'architecture IA-32. Intel a introduit SSE3 au d\u00E9but de l'ann\u00E9e 2004 avec la version Prescott de son processeur Pentium 4. En avril 2005, AMD a introduit un sous-ensemble de SSE3 dans la r\u00E9vision E de leur processeur Athlon 64 (Venice et San Diego). Leur jeu d'instructions SIMD pour la plate-forme x86, du plus ancien au plus r\u00E9cent, sont MMX, 3DNow! (d\u00E9velopp\u00E9 par AMD), SSE et SSE2."@fr . . . "Die Streaming SIMD Extensions 3 (kurz SSE3) ist die zweite Erweiterung des SSE-Befehlssatzes. Sie ist auch unter dem Intel-Codenamen Prescott New Instructions (PNI) bekannt, da sie zuerst bei der Prescott-Variante des Pentium 4 ab Fr\u00FChjahr 2004 verwendet wurde. AMD unterst\u00FCtzt diese Erweiterungen seit April 2005 und f\u00FChrte diese mit den E-Steppings beim Athlon 64, Opteron und Sempron ein. VIA bzw. Centaur unterst\u00FCtzen mit dem C7 ebenfalls die neuen Befehle. SSE3 erweitert den SSE2-Befehlssatz um 13 neue Instruktionen:"@de . . "SSE3"@zh . . . . . . . "SSE3 Conocido por el nombre en c\u00F3digo que le puso Intel, Prescott New Instructions (PNI) es la tercera generaci\u00F3n de las instrucciones SSE para la arquitectura IA-32. Intel mostr\u00F3 las SSE3 a principios de 2004 con la revisi\u00F3n de su CPU Pentium 4 llamada Prescott. En abril de 2005 AMD sac\u00F3 una parte del SSE3 en la revisi\u00F3n E (llamadas Venice y San Diego) de su CPU Athlon 64. SSE3 a\u00F1ade 13 nuevas instrucciones a SSE2."@es . . .