. "\u56FA\u5B9A\u578B\u6545\u969C"@zh . . . "A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an input is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the input could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.Not all faults can be analyzed using the stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model. Also, redundant circuits cannot be tested using this model, since by design there is no change in any output as a result of a single fault."@en . . "4782"^^ . "Stuck-at fault"@en . . . . "\u56FA\u5B9A\u578B\u6545\u969C\uFF08stuck-at fault\uFF09\u4E5F\u7A31\u70BA\u9ECF\u8457\u6027\u6545\u969C\uFF0C\u662F\u4FE1\u865F\u6216\u662F\u91DD\u8173\u56FA\u5B9A\u5728\u908F\u8F2F\u7684\u9AD8\u96FB\u4F4D\u3001\u4F4E\u96FB\u4F4D\uFF0C\u6216\u662F\u9AD8\u963B\u6001\u7684\uFF0C\u6545\u969C\u6A21\u64EC\u5668\u6216\u662FATPG\u6703\u7528\u9019\u6545\u969C\u4F86\u6A21\u64EC\u96C6\u6210\u7535\u8DEF\u4E2D\u7684\u88FD\u7A0B\u7455\u75B5\u3002\u5728\u6E2C\u8A66\u6642\uFF0C\u6703\u5C07\u4FE1\u865F\u7DAD\u6301\u5728\u9AD8\u96FB\u4F4D\u4E00\u6BB5\u6642\u9593\uFF0C\u78BA\u5B9A\u6B64\u4FE1\u865F\u4E0D\u6703\u56FA\u5B9A\u5728\u4F4E\u96FB\u4F4D\uFF0C\u4E5F\u6703\u5C07\u4FE1\u865F\u7DAD\u6301\u5728\u4F4E\u96FB\u4F4D\u4E00\u6BB5\u6642\u9593\uFF0C\u78BA\u5B9A\u6B64\u4FE1\u865F\u4E0D\u6703\u56FA\u5B9A\u5728\u9AD8\u96FB\u4F4D\u3002 \u56FA\u5B9A\u578B\u6545\u969C\u53EA\u80FD\u7528\u4F86\u5206\u6790\u90E8\u4EFD\u7684\u6545\u969C\uFF0C\u91DD\u5C0D\u975C\u614B\u5192\u96AA\uFF08\u5373\u5206\u652F\u4FE1\u865F\uFF09\u7684\u88DC\u511F\u4FE1\u865F\u6703\u8B93\u6B64\u4FE1\u865F\u7121\u6CD5\u7528\u56FA\u5B9A\u578B\u6545\u969C\u6A21\u578B\u9032\u884C\u6E2C\u8A66\uFF0C\u800C\u5197\u9918\u578B\u96FB\u8DEF\u4E5F\u7121\u6CD5\u7528\u6B64\u6A21\u578B\u9032\u884C\u6E2C\u8A66\uFF0C\u56E0\u70BA\u4F9D\u7167\u8A2D\u8A08\uFF0C\u82E5\u53EA\u6709\u55AE\u4E00\u6545\u969C\uFF0C\u4E0D\u6703\u56E0\u6B64\u5F71\u97FF\u8F38\u51FA\u4FE1\u865F\u3002"@zh . . . . . "943909931"^^ . . . "\u56FA\u5B9A\u578B\u6545\u969C\uFF08stuck-at fault\uFF09\u4E5F\u7A31\u70BA\u9ECF\u8457\u6027\u6545\u969C\uFF0C\u662F\u4FE1\u865F\u6216\u662F\u91DD\u8173\u56FA\u5B9A\u5728\u908F\u8F2F\u7684\u9AD8\u96FB\u4F4D\u3001\u4F4E\u96FB\u4F4D\uFF0C\u6216\u662F\u9AD8\u963B\u6001\u7684\uFF0C\u6545\u969C\u6A21\u64EC\u5668\u6216\u662FATPG\u6703\u7528\u9019\u6545\u969C\u4F86\u6A21\u64EC\u96C6\u6210\u7535\u8DEF\u4E2D\u7684\u88FD\u7A0B\u7455\u75B5\u3002\u5728\u6E2C\u8A66\u6642\uFF0C\u6703\u5C07\u4FE1\u865F\u7DAD\u6301\u5728\u9AD8\u96FB\u4F4D\u4E00\u6BB5\u6642\u9593\uFF0C\u78BA\u5B9A\u6B64\u4FE1\u865F\u4E0D\u6703\u56FA\u5B9A\u5728\u4F4E\u96FB\u4F4D\uFF0C\u4E5F\u6703\u5C07\u4FE1\u865F\u7DAD\u6301\u5728\u4F4E\u96FB\u4F4D\u4E00\u6BB5\u6642\u9593\uFF0C\u78BA\u5B9A\u6B64\u4FE1\u865F\u4E0D\u6703\u56FA\u5B9A\u5728\u9AD8\u96FB\u4F4D\u3002 \u56FA\u5B9A\u578B\u6545\u969C\u53EA\u80FD\u7528\u4F86\u5206\u6790\u90E8\u4EFD\u7684\u6545\u969C\uFF0C\u91DD\u5C0D\u975C\u614B\u5192\u96AA\uFF08\u5373\u5206\u652F\u4FE1\u865F\uFF09\u7684\u88DC\u511F\u4FE1\u865F\u6703\u8B93\u6B64\u4FE1\u865F\u7121\u6CD5\u7528\u56FA\u5B9A\u578B\u6545\u969C\u6A21\u578B\u9032\u884C\u6E2C\u8A66\uFF0C\u800C\u5197\u9918\u578B\u96FB\u8DEF\u4E5F\u7121\u6CD5\u7528\u6B64\u6A21\u578B\u9032\u884C\u6E2C\u8A66\uFF0C\u56E0\u70BA\u4F9D\u7167\u8A2D\u8A08\uFF0C\u82E5\u53EA\u6709\u55AE\u4E00\u6545\u969C\uFF0C\u4E0D\u6703\u56E0\u6B64\u5F71\u97FF\u8F38\u51FA\u4FE1\u865F\u3002"@zh . . . . . "A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. For example, an input is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the input could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.Not all faults can be analyzed using the stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model. Also, redundant circuits cannot be tested using this mo"@en . . . . . "2438898"^^ . . . . . . .