"1058678416"^^ . . . . . . "\uD0C0\uC77C64\uB294 \uC5D0\uC11C \uC0DD\uC0B0\uD558\uB294 90~45 \uB098\uB178\uBBF8\uD130 \uACF5\uC815\uC758 \uAE30\uBC18\uC758 64\uCF54\uC5B4 \uB9C8\uC774\uD06C\uB85C\uD504\uB85C\uC138\uC11C\uC774\uBA702\uAC1C\uC758 DDR2 \uBA54\uBAA8\uB9AC \uCEE8\uD2B8\uB864\uB7EC, 2\uAC1C\uC758 \uAE30\uAC00\uBE44\uD2B8\uAE09 , 2\uAC1C\uC758 10\uAE30\uAC00\uBE44\uD2B8\uAE09 \uB4F1\uC758 I/O\uC778\uD130\uD398\uC774\uC2A4\uAC00 \uB9C8\uC774\uD06C\uB85C\uD504\uB85C\uC138\uC11C\uB0B4\uC5D0 \uB0B4\uC7A5\uB418\uC5B4 \uC788\uC5B4, \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB098 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0 \uB4F1\uC758 \uCE69\uC14B\uC740 \uD544\uC694\uAC00 \uC5C6\uB2E4. \uC774 \uB9C8\uC774\uD06C\uB85C\uD504\uB85C\uC138\uC11C\uB294 \uC11C\uBC84\uB098 \uC6CC\uD06C\uC2A4\uD14C\uC774\uC158\uAE09\uC758 \uCEF4\uD4E8\uD130\uC5D0 \uC4F0\uC774\uAC8C \uB41C\uB2E4. \uB610\uD55C 8x8\uC758 \uACA9\uC790\uBAA8\uC591\uC73C\uB85C \uCF54\uC5B4\uB97C \uB298\uC5B4\uB193\uC544 \uAC01 \uCF54\uC5B4\uAC04\uC758 \uD1B5\uC2E0\uC758 \uC9C0\uC5F0\uC2DC\uAC04\uC744 \uC0AD\uAC10\uC2DC\uD0AC \uC218 \uC788\uB2E4. \uCF54\uC5B4\uB2F9 \uC18C\uBAA8\uC804\uB825\uC740 170mW ~ 300mW, \uAC01 \uCF54\uC5B4\uB2F9 \uB3C5\uB9BD\uC801\uC73C\uB85C \uB9AC\uB205\uC2A4\uB098 \uB2E4\uB978 \uC6B4\uC601\uCCB4\uC81C\uB97C \uAD6C\uB3D9 \uD560 \uC218\uB3C4 \uC788\uACE0, \uCF54\uC5B4\uB97C \uBAA8\uC544\uC11C \uBA40\uD2F0\uC4F0\uB808\uB529\uC73C\uB85C \uC6B4\uC601\uCCB4\uC81C\uB97C \uC791\uB3D9\uC2DC\uD0AC \uC218\uB3C4 \uC788\uB2E4. \uC774\uCC98\uB7FC \uB2E4\uC218\uC758 \uD504\uB85C\uC138\uC11C\uB97C \uC9D1\uC801\uD558\uB294 \uACBD\uC6B0, \uD504\uB85C\uC138\uC11C\uC758 \uC18D\uB3C4\uB97C \uC62C\uB9AC\uB294 \uAC83\uBCF4\uB2E4 \uD504\uB85C\uC138\uC11C\uC758 \uC218\uB97C \uC99D\uAC00\uC2DC\uCF1C \uC131\uB2A5 \uD5A5\uC0C1\uC744 \uB3C4\uBAA8\uD558\uAE30 \uB54C\uBB38\uC5D0 \uAC01 \uCF54\uC5B4\uC758 \uC18D\uB3C4\uBCF4\uB2E4\uB294 \uACF5\uAC04\uACFC \uC804\uB825 \uC18C\uBAA8\uAC00 \uC911\uC694\uD55C \uC694\uC18C\uAC00 \uB41C\uB2E4."@ko . "TILE64 \u00E8 un microcontrollore sviluppato dalla Tilera Corporation. Il microcontrollore \u00E8 formato da 64 processori elementari chiamati \"Tile\" collegati da una . Ogni tile include un core di calcolo, una propria cache e un router non bloccante utilizzato per smistare le comunicazioni tra i tile del processore. La rete permette una velocit\u00E0 di comunicazione massima di 500 Gbit tra un tile e i quattro tile adiacenti."@it . . "900"^^ . . "MHz"@en . . . . "45.0"^^ . . . . "2013-01-19"^^ . . . . . . "2007"^^ . . . . . "Chipmakers aim to unclog data paths"@en . . "TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 \"tiles\", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. The short-pipeline, in-order, three-issue cores implement a MIPS-inspired VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores (\"tile\") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches. A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a \"flexible\" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz. According to CTO and co-founder Anant Agarwal, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high. Support for the TILE64 architecture was added to Linux kernel version 2.6.36 but was dropped in kernel version 4.16. A non-official LLVM back-end for Tilera exists."@en . . "TILE64"@it . . "TILE64"@en . . . . . . . "12862300"^^ . . . . "\uD0C0\uC77C64\uB294 \uC5D0\uC11C \uC0DD\uC0B0\uD558\uB294 90~45 \uB098\uB178\uBBF8\uD130 \uACF5\uC815\uC758 \uAE30\uBC18\uC758 64\uCF54\uC5B4 \uB9C8\uC774\uD06C\uB85C\uD504\uB85C\uC138\uC11C\uC774\uBA702\uAC1C\uC758 DDR2 \uBA54\uBAA8\uB9AC \uCEE8\uD2B8\uB864\uB7EC, 2\uAC1C\uC758 \uAE30\uAC00\uBE44\uD2B8\uAE09 , 2\uAC1C\uC758 10\uAE30\uAC00\uBE44\uD2B8\uAE09 \uB4F1\uC758 I/O\uC778\uD130\uD398\uC774\uC2A4\uAC00 \uB9C8\uC774\uD06C\uB85C\uD504\uB85C\uC138\uC11C\uB0B4\uC5D0 \uB0B4\uC7A5\uB418\uC5B4 \uC788\uC5B4, \uB178\uC2A4\uBE0C\uB9AC\uC9C0\uB098 \uC0AC\uC6B0\uC2A4\uBE0C\uB9AC\uC9C0 \uB4F1\uC758 \uCE69\uC14B\uC740 \uD544\uC694\uAC00 \uC5C6\uB2E4. \uC774 \uB9C8\uC774\uD06C\uB85C\uD504\uB85C\uC138\uC11C\uB294 \uC11C\uBC84\uB098 \uC6CC\uD06C\uC2A4\uD14C\uC774\uC158\uAE09\uC758 \uCEF4\uD4E8\uD130\uC5D0 \uC4F0\uC774\uAC8C \uB41C\uB2E4. \uB610\uD55C 8x8\uC758 \uACA9\uC790\uBAA8\uC591\uC73C\uB85C \uCF54\uC5B4\uB97C \uB298\uC5B4\uB193\uC544 \uAC01 \uCF54\uC5B4\uAC04\uC758 \uD1B5\uC2E0\uC758 \uC9C0\uC5F0\uC2DC\uAC04\uC744 \uC0AD\uAC10\uC2DC\uD0AC \uC218 \uC788\uB2E4. \uCF54\uC5B4\uB2F9 \uC18C\uBAA8\uC804\uB825\uC740 170mW ~ 300mW, \uAC01 \uCF54\uC5B4\uB2F9 \uB3C5\uB9BD\uC801\uC73C\uB85C \uB9AC\uB205\uC2A4\uB098 \uB2E4\uB978 \uC6B4\uC601\uCCB4\uC81C\uB97C \uAD6C\uB3D9 \uD560 \uC218\uB3C4 \uC788\uACE0, \uCF54\uC5B4\uB97C \uBAA8\uC544\uC11C \uBA40\uD2F0\uC4F0\uB808\uB529\uC73C\uB85C \uC6B4\uC601\uCCB4\uC81C\uB97C \uC791\uB3D9\uC2DC\uD0AC \uC218\uB3C4 \uC788\uB2E4. \uC774\uCC98\uB7FC \uB2E4\uC218\uC758 \uD504\uB85C\uC138\uC11C\uB97C \uC9D1\uC801\uD558\uB294 \uACBD\uC6B0, \uD504\uB85C\uC138\uC11C\uC758 \uC18D\uB3C4\uB97C \uC62C\uB9AC\uB294 \uAC83\uBCF4\uB2E4 \uD504\uB85C\uC138\uC11C\uC758 \uC218\uB97C \uC99D\uAC00\uC2DC\uCF1C \uC131\uB2A5 \uD5A5\uC0C1\uC744 \uB3C4\uBAA8\uD558\uAE30 \uB54C\uBB38\uC5D0 \uAC01 \uCF54\uC5B4\uC758 \uC18D\uB3C4\uBCF4\uB2E4\uB294 \uACF5\uAC04\uACFC \uC804\uB825 \uC18C\uBAA8\uAC00 \uC911\uC694\uD55C \uC694\uC18C\uAC00 \uB41C\uB2E4."@ko . "90.0"^^ . . . . . . "TILE64"@en . . "TILE64 \u00E8 un microcontrollore sviluppato dalla Tilera Corporation. Il microcontrollore \u00E8 formato da 64 processori elementari chiamati \"Tile\" collegati da una . Ogni tile include un core di calcolo, una propria cache e un router non bloccante utilizzato per smistare le comunicazioni tra i tile del processore. La rete permette una velocit\u00E0 di comunicazione massima di 500 Gbit tra un tile e i quattro tile adiacenti. Ogni core ha una pipeline corta a tre stadi in grado di eseguire un set di istruzioni in ordine derivate da quelle dell'architettura MIPS ma estese per essere istruzioni VLIW. Ogni core ha una serie di registro e tre unit\u00E0 funzionali, due ALU per gli interi e un'unit\u00E0 load-store. Ogni tile ha una cache L1 da 8 KB per i dati, 8 KB per le istruzioni e una cache L2 da 64 KB. I tile possono vedere una cache L3 formata da tutte le cache L2 dei core da 5 MB. Ogni tile pu\u00F2 eseguire un sistema operativo completo e pi\u00F9 core possono essere combinati per eseguire un sistema operativo in modalit\u00E0 SMP. Mediamente ogni tile consuma 300 milliWatt e il processore complessivamente pu\u00F2 sviluppare di picco 192 miliardi di operazioni su interi al secondo. Il TILE64 ha quattro controller DDR2, due interfacce Ethernet da 10 Gigabit, due interfacce PCI e un'interfaccia di input/output flessibile che pu\u00F2 essere programmata per gestire molteplici protocolli. Il processore \u00E8 prodotto con un processo a 90 nm e con frequenze di funzionamento comprese tra i 600 e i 900 MHz. Secondo il CTO e cofondatore , Tilera mira a produrre processori per dispositivi di rete e per dispositivi video, mercati che richiedono elevate potenze di calcolo e non necessitano di compatibilit\u00E0 con le architetture X86."@it . . . "TILE64 is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 \"tiles\", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor. TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a \"flexible\" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz."@en . "5221"^^ . . . . . "MHz"@en . . . . . . . . . "600"^^ . . . "64"^^ . "\uD0C0\uC77C64"@ko . . . . . . .