"1062479451"^^ . "Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format."@en . . . . "Verilog-A"@es . . . "Verilog-A es un lenguaje de modelamiento est\u00E1ndar en la industria para circuitos anal\u00F3gicos. Es un 'subset' de Verilog-AMS con la caracter\u00EDstica de ser continuo a trav\u00E9s del tiempo."@es . . . . . . "Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS. A few commercial applications may export MEMS designs in Verilog-A format."@en . "Verilog-A es un lenguaje de modelamiento est\u00E1ndar en la industria para circuitos anal\u00F3gicos. Es un 'subset' de Verilog-AMS con la caracter\u00EDstica de ser continuo a trav\u00E9s del tiempo."@es . . . . . . . . . . "Verilog-A\u662F\u4E00\u79CD\u9488\u5BF9\u6A21\u62DF\u7535\u8DEF\u7684\u5DE5\u4E1A\u6807\u51C6\u6A21\u578B\u8BED\u8A00\uFF0C\u5B83\u662F Verilog-AMS\u7684\u8FDE\u7EED\u65F6\u95F4\u5B50\u96C6\u3002 Verilog-A\u88AB\u8BBE\u8BA1\u7528\u6765\u5BF9Spectre\u7535\u8DEF\u4EFF\u771F\u5668\uFF08Spectre Circuit Simulator\uFF09\u7684\u884C\u4E3A\u7EA7\u63CF\u8FF0\u8FDB\u884C\u6807\u51C6\u5316\uFF0C\u4EE5\u5B9E\u73B0\u4E0EVHDL\uFF08\u53E6\u4E00\u4E2AIEEE\u6807\u51C6\u652F\u6301\u7684\u786C\u4EF6\u63CF\u8FF0\u8BED\u8A00\uFF09\u3002\u5B83\u4ECE\u5176\u4ED6\u8BED\u8A00\uFF08\u4F8B\u5982MAST\uFF09\u5438\u6536\u4E86\u5BF9\u6A21\u62DF\u7535\u8DEF\u7684\u652F\u6301\u3002\u56FD\u9645Verilog\u5F00\u653E\u7EC4\u7EC7\uFF08Open Verilog International, OVI\uFF09\u652F\u6301 Verilog\u7684\u6807\u51C6\u5316\uFF0C\u4F7F\u5F97Verilog-A\u4F5C\u4E3A\u6574\u4E2AVerilog-AMS\u8BA1\u5212\u7684\u4E00\u90E8\u5206\uFF0C\u4ECE\u800C\u5B9E\u73B0\u5BF9\u6A21\u62DF\u7535\u8DEF\u548C\u6570\u5B57\u7535\u8DEF\u8BBE\u8BA1\u7684\u5904\u7406\u80FD\u529B\u3002Verilog-A\u662FVerilog-AMS\u9879\u76EE\u7684\u6700\u521D\u9636\u6BB5\u53D1\u5C55\u8D77\u6765\u7684\u3002 \u4E0D\u8FC7\uFF0CVerilog\u7684\u5F00\u53D1\u8FDB\u5C55\u4E0EVerilog-AMS\u5EF6\u8FDF\u4E0D\u540C\uFF0C\u800C\u5F53\u65F6Verilog\u88AB\u7EB3\u5165\u4E86IEEE 1364\u6807\u51C6\uFF0C\u8FD9\u5C31\u4F7F\u5F97Verilog-AMS\u88AB\u9057\u7559\u7ED9\u4E86Accellera\u516C\u53F8\u3002\u56E0\u6B64\u6700\u521D\u7684\u5355\u4E00\u8BED\u8A00\u6807\u51C6\u7684\u76EE\u6807\u5E76\u6CA1\u6709\u5B9E\u73B0\u3002"@zh . . . . . . "Verilog-A"@en . . "Verilog-A\u662F\u4E00\u79CD\u9488\u5BF9\u6A21\u62DF\u7535\u8DEF\u7684\u5DE5\u4E1A\u6807\u51C6\u6A21\u578B\u8BED\u8A00\uFF0C\u5B83\u662F Verilog-AMS\u7684\u8FDE\u7EED\u65F6\u95F4\u5B50\u96C6\u3002 Verilog-A\u88AB\u8BBE\u8BA1\u7528\u6765\u5BF9Spectre\u7535\u8DEF\u4EFF\u771F\u5668\uFF08Spectre Circuit Simulator\uFF09\u7684\u884C\u4E3A\u7EA7\u63CF\u8FF0\u8FDB\u884C\u6807\u51C6\u5316\uFF0C\u4EE5\u5B9E\u73B0\u4E0EVHDL\uFF08\u53E6\u4E00\u4E2AIEEE\u6807\u51C6\u652F\u6301\u7684\u786C\u4EF6\u63CF\u8FF0\u8BED\u8A00\uFF09\u3002\u5B83\u4ECE\u5176\u4ED6\u8BED\u8A00\uFF08\u4F8B\u5982MAST\uFF09\u5438\u6536\u4E86\u5BF9\u6A21\u62DF\u7535\u8DEF\u7684\u652F\u6301\u3002\u56FD\u9645Verilog\u5F00\u653E\u7EC4\u7EC7\uFF08Open Verilog International, OVI\uFF09\u652F\u6301 Verilog\u7684\u6807\u51C6\u5316\uFF0C\u4F7F\u5F97Verilog-A\u4F5C\u4E3A\u6574\u4E2AVerilog-AMS\u8BA1\u5212\u7684\u4E00\u90E8\u5206\uFF0C\u4ECE\u800C\u5B9E\u73B0\u5BF9\u6A21\u62DF\u7535\u8DEF\u548C\u6570\u5B57\u7535\u8DEF\u8BBE\u8BA1\u7684\u5904\u7406\u80FD\u529B\u3002Verilog-A\u662FVerilog-AMS\u9879\u76EE\u7684\u6700\u521D\u9636\u6BB5\u53D1\u5C55\u8D77\u6765\u7684\u3002 \u4E0D\u8FC7\uFF0CVerilog\u7684\u5F00\u53D1\u8FDB\u5C55\u4E0EVerilog-AMS\u5EF6\u8FDF\u4E0D\u540C\uFF0C\u800C\u5F53\u65F6Verilog\u88AB\u7EB3\u5165\u4E86IEEE 1364\u6807\u51C6\uFF0C\u8FD9\u5C31\u4F7F\u5F97Verilog-AMS\u88AB\u9057\u7559\u7ED9\u4E86Accellera\u516C\u53F8\u3002\u56E0\u6B64\u6700\u521D\u7684\u5355\u4E00\u8BED\u8A00\u6807\u51C6\u7684\u76EE\u6807\u5E76\u6CA1\u6709\u5B9E\u73B0\u3002"@zh . . . . . . . . . . . . . . "5555"^^ . . . . "Verilog-A"@zh . "7649454"^^ .