About: Infineon TriCore

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TriCore is a 32-bit microcontroller architecture from Infineon. It unites the elements of a RISC processor core, a microcontroller and a DSP in one chip package.

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rdf:type	company yago:Architecture102734725 yago:Artifact100021939 yago:Building102913152 yago:Object100002684 yago:PhysicalEntity100001930 yago:YagoGeoEntity yago:YagoPermanentlyLocatedEntity yago:Structure104341686 yago:Whole100003553
rdfs:label	Infineon TriCore (de) Infineon TriCore (en)
rdfs:comment	TriCore ist die Bezeichnung einer 32-Bit-Prozessorarchitektur der Firma Infineon Technologies AG. (de) TriCore is a 32-bit microcontroller architecture from Infineon. It unites the elements of a RISC processor core, a microcontroller and a DSP in one chip package. (en)
foaf:homepage	http://www.infineon.com/microcontroller
name	TriCore (en)
dcterms:subject	Digital signal processors Microcontrollers
Wikipage page ID	2822564 (xsd:integer)
Wikipage revision ID	1026902384 (xsd:integer)
Link from a Wikipage to another Wikipage	Engine control unit Electric vehicles Chip carrier Load–store architecture 32-bit 32-bit computing Microcontroller Hybrid vehicle AUTOSAR Digital signal processors Microcontrollers Digital signal processing Digital signal processor Infineon Technologies CPU RISC Microcontroller unit Infineon
Link from a Wikipage to an external page	http://www.hightec-rt.com/en/downloads/sources.html http://www.infineon.com/microcontroller
sameAs	Infineon TriCore Infineon TriCore Infineon TriCore Infineon TriCore
dbp:wikiPageUsesTemplate	dbt:Microcontrollers dbt:Redirect dbt:Reflist dbt:Infobox_CPU_architecture dbt:Compu-stub
design	RISC
designer	Infineon Technologies AG (en)
introduced	1999 (xsd:integer)
open	No (en)
type	Load–store architecture
version	2 (xsd:integer)
has abstract	TriCore ist die Bezeichnung einer 32-Bit-Prozessorarchitektur der Firma Infineon Technologies AG. (de) TriCore is a 32-bit microcontroller architecture from Infineon. It unites the elements of a RISC processor core, a microcontroller and a DSP in one chip package. (en)
bits	32 (xsd:integer)
endianness	Little for data memory and CPU registers (en)
registers	16 (xsd:integer)
gold:hypernym	Architecture
prov:wasDerivedFrom	wikipedia-en:Infineon_TriCore?oldid=1026902384&ns=0
page length (characters) of wiki page	3537 (xsd:nonNegativeInteger)
foaf:isPrimaryTopicOf	wikipedia-en:Infineon_TriCore
is Link from a Wikipage to another Wikipage of	32-bit computing Executable and Linkable Format TASKING CODESYS TriCore Tricore
is Wikipage redirect of	TriCore Tricore
is foaf:primaryTopic of	wikipedia-en:Infineon_TriCore

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